Isolation method for semiconductor device using selective epitax

Details Isolation method for semiconductor device using selective epitax Isolation method for semiconductor device using selective epitax

1997-08-21

1999-07-20

Dutton, Brian

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

438422, H01L 2176

Patent

active

059267216

ABSTRACT:
An isolation method for a highly-integrated semiconductor device includes growing an epitaxial layer on the entire surface of a semiconductor substrate including over a trench on which an oxide layer is formed, thereby leaving the inside of the trench empty. A portion of the epitaxial layer which is located over the trench is then oxidized to form an isolation region.

REFERENCES:
patent: 4169000 (1979-09-01), Riseman
patent: 4356211 (1982-10-01), Riseman
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5353861 (1994-10-01), Bashir et al.
"Deep Trench Well Isolation for 256kB 6T CMOS Static RAM", VLSI 85, by Kazuhito Hashimoto, 1985 (pp. 94 & 95).

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