Isolation layer for CMOS image sensor and fabrication method...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S200000, C438S060000, C438S073000, C438S075000, C438S142000, C438S192000, C257S446000, C257S291000, C257S292000, C257S293000, C257S443000

Reexamination Certificate

active

07135362

ABSTRACT:
The present invention relates to an isolation layer for CMOS image sensor and a fabrication method thereof, which are capable of improving a low light level characteristic of the CMOS image sensor. The isolation layer includes: a field insulating layer formed on a predetermined portion of a substrate in the logic area to thereby define an active area and a field area; a field stop ion implantation area formed on a predetermined portion of the substrate in the pixel area, the field stop ion implantation area having a predetermined depth from a surface of the substrate to define an active area and a field area; and an oxide layer deposited on a substrate surface corresponding to the field stop ion implantation area.

REFERENCES:
patent: 6291280 (2001-09-01), Rhodes
patent: 6329218 (2001-12-01), Pan
patent: 6344669 (2002-02-01), Pan
patent: 6563187 (2003-05-01), Park
patent: 6583484 (2003-06-01), Pan et al.
patent: 2003-0058291 (2003-07-01), None
Korean Notice of Preliminary Rejection dated Sep. 27, 2005 for KR 2003-0075963, filed Oct. 29, 2003.

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