Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-07-17
1999-12-14
Booth, Richard
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438693, H01L 214763
Patent
active
060017317
ABSTRACT:
A method for providing a chemical mechanical polishing planarization process for preventing multi-polysilicon and multi-metal level electrical shorts, which includes briefly the sequential processing steps of i) providing an insulating layer to a first thickness over a device wafer with non-planar surface topography; ii) chemical-mechanical polishing the first insulating layer; and iii) deposition of another polysilicon layer of second thickness to prevent the barely exposed or exposed underlying polysilicon from shorting to the next polysilicon or metal level of interconnects.
REFERENCES:
patent: 4614021 (1986-09-01), Hulseweh
patent: 5395801 (1995-03-01), Doan et al.
patent: 5420075 (1995-05-01), Homma et al.
patent: 5677239 (1997-10-01), Isobe
Liang Mong-Song
Su Chung-Hui
Wang Chen-Jong
Wuu Shou-Gwo
Ackerman Stephen B.
Booth Richard
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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