Isolated SOI memory structure with vertically formed transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257296, 257300, 257301, 257302, 257303, 257509, 257510, 438296, 438359, 438391, H01C 2120

Patent

active

059593229

ABSTRACT:
A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a compacitor comprising a first electrode connected with the first impurity region of the transistor and a second electrode formed on the first electrode with a dielectric film disposed therebetween, wherein a channel region formed between the first impurity region and the second impurity region of the transistor is vertically located on the capacitor, and a contact hole connecting the second impurity region of the transistor with the bit-line is vertically located on the channel region, thus achieving the cell area required for one-giga-bit memory devices and beyond and enabling increased capacitance.

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Sunouchi, K. et al., A Surrounding Gate Transistor (SGT) Cell for 64/256Mbit DRAMs, 1989 IEEE, IEDM 89-23-IEDM 89-26.
Nishihara, Toshiyuki et al., A Buried Capacitor DRAM Cell with Bonded SOI for 256M and 1Gbit DRAMs, 1992 IEEE, IEDM 92-803-IEDM 92-806.
Ozaki, T. et al., A Surrounding Isolation-Merged Plate Electrode (SIMPLE) Cell with checkered layout for 256Mbit DRAMs and beyond, 1991 IEEE, IEDM 91-469-IEDM 91-472.

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