Isolated high voltage PMOS transistor

Details Isolated high voltage PMOS transistor Isolated high voltage PMOS transistor

2002-10-25

2004-06-15

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257S337000, C257S344000, C257S355000, C257S356000, C257S357000

Reexamination Certificate

active

06750489

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor structures. More particularly, the present invention relates to MOS transistor structures.
2. The Prior Art
The device of the present invention is a DMOS (Double diffused Metal Oxide Semiconductor) transistor. Several techniques are known for building DMOS transistors in CMOS (Complementary Metal Oxide Semiconductor) and in BiCMOS (Bipolar CMOS) processes.
U.S. Pat. No. 6,218,228 to Zambrano teaches a lightly doped region for a DMOS transistor but it is a vertically oriented structure that is not compatible with CMOS.
U.S. Pat. No. 6,048,759 to Hshieh teaches a similar structure but does not teach lightly doped. It is also a vertical device.
U.S. Pat. No. 5,550,067 to Kuroyanagi teaches a lightly doped region but without isolation. This requires that the N-type DMOS transistors that are in the process have a lightly doped well. This limits performance of the NMOS (n-type MOS) transistors on the same die.
U.S. Pat. No. 5,317,180 to Hutter teaches a BiCMOS process but does not teach use of a lightly doped region.
U.S. Pat. No. 5,055,896 to Williams teaches a vertical device that is not CMOS compatible. Isolation is not taught or suggested.
BRIEF DESCRIPTION OF THE INVENTION
An isolated high-voltage P-type DMOS transistor comprises a layer of p-type semiconductor material in which a first n-well is disposed at an axis of symmetry. A first shallow trench isolation region is disposed in the first n-well about the axis of symmetry and forms a source for the transistor.
A first annular shallow trench isolation region is disposed in the layer of p-type semiconductor material about the axis of symmetry and spaced outwardly from an outer perimeter of the first annular p-type region, a distance between an inner perimeter of the first shallow trench isolation region and an outer perimeter of the first annular p-type region defining a channel length of the transistor.
An annular p-well region is disposed in the layer of p-type semiconductor material about the axis of symmetry and spaced outwardly from the inner perimeter of the first shallow trench isolation region. An inner perimeter of the annular p-well region is disposed outside of the inner perimeter of the first annular p-type region at a distance such that lateral diffusion of the p-well impurity begins to increase a surface impurity concentration in the layer of p-type semiconductor material at the inner periphery of the first shallow trench isolation region.
A second annular p-type region is disposed in the p-well about the axis of symmetry and outside of the outer perimeter of the first shallow trench isolation region to form the drain of the transistor. An annular gate is disposed above and insulated from the layer of p-type semiconductor material. The gate has an inner perimeter aligned with the outer perimeter of the first annular p-type region and an outer perimeter disposed over the first shallow trench isolation region.
A second annular n-well region is disposed in the layer of p-type semiconductor layer about the axis of symmetry and outside of a second annular shallow trench isolation region. The second annular n-well provides a contact to buried annular n-type contact regions which in turn contact a buried n-type semiconductor layer within the p-type semiconductor layer. The second n-well, the buried annular contacts and the n-type buried layer form a junction isolation structure of the transistor from the substrate. The second annular shallow trench isolation region is disposed in the layer of p-type semiconductor layer about the axis of symmetry and outside of the annular p-well region to form an isolation region between the potential of the drain and the isolation structure. A third shallow trench isolation structure is disposed in the layer of p-type semiconductor layer about the axis of symmetry and outside of the annular second n-well structure. The body contact for the p-type DMOS transistor is an n+ diffusion placed in the first n-well at the axis of symmetry.
According to one illustrative embodiment of the invention, the layer of p-type semiconductor material may be a semiconductor substrate. According to other illustrative embodiments of the invention, the layer of p-type semiconductor material may be an epitaxial layer disposed on a semiconductor substrate. An intervening epitaxial layer may be disposed between the substrate and the layer of p-type semiconductor material. Photodiodes may or may not be disposed in the semiconductor substrate and/or the epitaxial layers depending upon the application.


REFERENCES:
patent: 5055896 (1991-10-01), Williams et al.
patent: 5317180 (1994-05-01), Hutter et al.
patent: 5550067 (1996-08-01), Kuroyanagi et al.
patent: 6048759 (2000-04-01), Hshieh et al.
patent: 6172401 (2001-01-01), Brand
patent: 6218228 (2001-04-01), Zambrano
patent: 6256689 (2001-07-01), Khosrowpour
patent: 6271567 (2001-08-01), Pozzoni et al.
patent: 6318156 (2001-11-01), Dutton et al.
patent: 6327914 (2001-12-01), Dutton

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