Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-04-01
2004-06-29
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S686000
Reexamination Certificate
active
06756305
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to multi-chip devices, and specifically to a method of bonding and electrically connecting dice within a stacked-die assembly.
BACKGROUND INFORMATION
Programmable logic devices can operate at faster speeds by increasing semiconductor device density. Besides more densely mapping circuitry on two-dimensional layers of semiconductor dice, semiconductor density can be further increased by stacking semiconductor dice. Stacked-die assemblies permit a three-dimensional interconnection of circuitry and thereby an even greater semiconductor device density.
Various methods of interconnecting and bonding dice in stacked-die assemblies have been developed. Some of these methods involve bonding the dice using adhesives. The adhesives add to the volume of the die assemblies and limit the area available to interconnect the dice. Other methods use wire bonding to interconnect circuitry on different dice. The relatively large wire bonds limit the three-dimensional density of circuitry in the stacked-die assemblies. Other methods use micropad structures disposed on each die, wherein a micropad on one die comes into contact with a corresponding micropad on the other die when the two dice are stacked. Examples of micropad structures and stacked-die assembly processes are found in U.S. Pat. Nos. 6,271,059, 6,114,221, 6,410,431, 6,444,560, 6,245,594, 6,368,930, as well as in published U.S. patent application Ser. No. 2002/0064906. Some stacked-die assembly processes involve fusing micropads together at elevated temperatures. See, for example, the article by Banerjee et al., entitled “3D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration,” Proceedings of the IEEE, vol. 89, No. 5, May 2001.
An alternative to these methods is sought that permits high three-dimensional density of circuitry within a programmable logic device.
SUMMARY
A die assembly contains multiple stacked dice bonded together by a plurality of metal posts. A first die has a plurality of metal posts oriented orthogonally to a planar first outer surface of the first die. The metal posts protrude from the first die out beyond the first outer surface. Similarly, a second die has a plurality of metal posts protruding from a second outer surface of the second die. The first die is coupled to the second die in a stacked relation such that each metal post protruding from the first outer surface of the first die contacts a metal post protruding from the second outer surface of the second die. The metal posts are prepared so as to be oxide free. Then this stacking is performed in an oxygen-free atmosphere so that the metal posts of the first die are cold welded to the metal posts of the second die when the first and second dice are pressed together. After cold welding, the first die and the second die are held together without an adhesive by many weak covalent bonds between the metal posts. In one embodiment, the surface of the first die does not contact the surface of the second die at locations other than the metal posts. In addition to bonding the first and second dice together, contacting metal posts can be used to communicate electrical signals between the dice.
Semiconductor dice are stacked and bonded in a method that includes forming metal vias on a first die, and etching away a portion of the metal vias to form metal posts. The top protruding end of each of the metal posts is disposed below the outer surface of the first die. A layer of the first die is then etched away such that the protruding end of each of the metal posts protrudes out from the outer surface of the first die. The method further includes forming protruding metal posts on a second die in a similar manner. The first die and the second die are then stacked such that the protruding end of each metal post of the first die contacts the protruding end of a corresponding metal post of the second die. This stacking operation is performed in an oxygen-free atmosphere such that the protruding ends of the metal posts do not oxidize. Pressure is applied to compress the first die and the second die such that a cold weld is formed between each metal post of the first die and a corresponding metal post of the second die. In one embodiment, the pressure applied to compress the first die and the second die does not bring the first outer surface of the first die in contact with the second outer surface of the second die.
Additional novel aspects and embodiments are described in the detailed description below. The claims, and not this summary, define the scope of the invention.
REFERENCES:
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patent: 6114221 (2000-09-01), Tonti et al.
patent: 6245594 (2001-06-01), Wu et al.
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patent: 6368930 (2002-04-01), Enquist
patent: 6410431 (2002-06-01), Bertin et al.
patent: 6444560 (2002-09-01), Pogge et al.
patent: 6643434 (2003-11-01), Cayrefourcq et al.
patent: 2002/0064906 (2002-05-01), Enquist
Alex Romanelli, “Intel Stacks Flash Deck in its Favor,” Electronic News, Apr. 10, 2003, available from Reed Electronics Group @ http://www.e-insite.net/electronicnews/index.asp?layout=article&articleid=CA291318.
Liu Justin
Vu David
Wallace T. Lester
Xilinx , Inc.
Young Edel M.
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