Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-04
2004-11-23
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C438S270000, C438S271000, C438S589000, C438S151000, C257S329000, C257S330000, C257S331000, C257S369000, C257S347000, C257S350000, C257S351000, C257S345000
Reexamination Certificate
active
06821834
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the fabrication of a fin-type a metal oxide field effect transistor (MOS FET) integrated circuit (IC). In particular, it relates to placing the fins used to make fin-shaped MOS FET transistors on a substrate in a rectangular pattern of rows and columns and using adjacent fins as shields during irradiation with particles or light.
The continuing movement of integrated circuit technology toward smaller scales is making system level integration on a chip both possible and desirable. The conventional MOS transistor structure is a planer type in which current flows horizontally from source to drain. As transistor size shrinks to below about 0.1 &mgr;m, the channel controlled by the gate also shrinks and unwanted couplings occur between the source and the drain, which is known as the “short channel problem.” The short channel problem also increases power consumption and the difficulty of designing a properly functioning circuit.
A fin transistor (also known as a “pillar transistor”) increases the size of the channel and reduces or eliminates the adverse effects of a short channel. Fin transistors can achieve a higher performance of current derivability because a fin transistor has a greater current flow area surrounding the gate or it uses a double gate. There are many inventions for fin-type MOSFET structures but because that structure is different from conventional planar transistors, new layout rules and manufacturing methods must be used when it is formed into an integrated circuit.
Referring to
FIGS. 1
a
and
1
b
, fin-type MOS transistor
1
has substrate
2
that forms fin
3
having top
4
and two sidewalls
5
. Over top
4
and sidewalls
5
of fin
3
is gate oxide
6
which is coated with conductive gate
7
. Drain
8
and source
9
are on opposite sides of gate
7
at top
4
and sidewalls
5
of fin
3
. (See also FIG. 2
a
of U.S. Pat. No. 5,844,278.) Because there are current flow channels under gate oxide layer
6
at both top
4
and the two sidewalls
5
of fin
3
, this structure has an increased channel area which increases current gain.
FIGS. 1
c
and
1
d
show another kind of a fin-type MOS transistor. The transistor in
FIGS. 1
c
and
1
d
has two channel areas on the sidewalls but does not have a channel area on the top of the fin. This structure is known as a dual gate or double gate transistor.
FIGS. 2
a
and
2
b
illustrate another fin-type MOS transistor structure known as a surrounded gate transistor (SGT) or a vertical transistor. (See Takato et al., “High Performance CMOS surrounding Gates Transistor (SGT) for Ultra High Density LSIs,” pages 222-225, IEEE Electron Device Meeting (1988)). In
FIGS. 2
a
and
2
b
, fin transistor
10
has substrate
11
which forms fin
12
. Fin
12
is surrounded by gate oxide
13
, which is covered by gate electrode
14
. Drain
15
is at the top of fin
12
and source
16
covers substrate
11
. Current flows through all four sidewall channels, which are controlled by surrounding gate electrode
14
.
The fins can be fabricated on a bulk silicon substrate or on an SOI (silicon on insulator) deposited silicon layer. The fins are formed by selectively etching the substrate using RIE (reactive ion etching) techniques or by depositing amorphous silicon by a conventional CVD (chemical vapor deposition) technique.,
FIGS. 3
a
to
3
c
show examples of conventional ion implantation processes for making planar silicon complementary metal oxide semiconductor (CMOS)large scale integrated circuits (LSI). In
FIG. 3
a
, N-type silicon substrate
17
has been coated with photoresist layer
18
, which has been exposed to light and etched away at
19
. Ion implantation with boron from the direction shown by the arrows creates P-type well
20
. In
FIG. 3
b
, substrate
21
of N-type silicon has been coated with a photoresist
22
which has been developed and etched away elsewhere. Gate oxide
23
and gate electrode
24
have been deposited and boron ion implantation from the direction of the arrows has formed a P-type diffusion layer
25
. The resulting P-channel transistor has source
26
and drain
27
.
In
FIG. 3
c
, boron ion implantation was used to create P-type well
28
in an N-type silicon substrate
29
and phosphorus or arsenic ion implantation formed source
30
and drain
31
.
SUMMARY OF INVENTION
An object of the present invention is to provide high performance, area-efficient fin-type MOS FET manufacturing methods, without the need for special processes, and to reduce the need for masking processes such as ion implantation.
Another object of the invention is to provide high performance, area-efficient fin-type MOS FET layout methods for large scale integrated circuits (LSI).
MOS FET ICs made according to the method of this invention have an ultra-high integration density and a higher performance for short channels and low operation voltages than ICs made with conventional planar type MOS FET transistors.
REFERENCES:
patent: 5844278 (1998-12-01), Mizuno et al.
patent: 6255699 (2001-07-01), Bracchitta et al.
patent: 6413802 (2002-07-01), Hu et al.
Fuerle Richard D.
Loke Steven
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