Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-04-21
2000-06-27
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438303, 438305, K01L 21336
Patent
active
06080629&
ABSTRACT:
A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.
REFERENCES:
patent: 4369072 (1983-01-01), Bakeman, Jr. et al.
patent: 4420872 (1983-12-01), Solo de Zaldivar
patent: 4481527 (1984-11-01), Chen et al.
patent: 4575921 (1986-03-01), Bhagat
patent: 4597159 (1986-07-01), Usami et al.
patent: 4774197 (1988-09-01), Haddad et al.
patent: 4869781 (1989-09-01), Euen et al.
patent: 4897368 (1990-01-01), Kobushi et al.
patent: 5518958 (1996-05-01), Giewont et al.
patent: 5567638 (1996-10-01), Lin et al.
patent: 5605848 (1997-02-01), Ngaoaram
patent: 5879975 (1999-03-01), Karlsson et al.
patent: 5885877 (1999-03-01), Gardner et al.
Silicon Processing for the VLSI Era--vol. 1: Process Technology, by S. Wolf, published by Lattice Press, Sunset Beach, CA, 1986, pp. 182-195, 209-211, 280-283, 294, 308, 321-327.
Silicon Processing for the VLSI Era--vol. 3: The Submicron MOSFET, by S. Wolf, published by Lattice Press, Sunset Beach, CA, 1995, pp. 641-642.
A. B. Joshi, J. Ahn, and D. L. Kwong; "Oxynitride Gate Dielectrics for p+-Polysilicon Gate MOS Devices," IEEE Electron Devices Letters, vol. 14, No. 12, Dec. 1993, pp. 560-562.
H. Fang et al., "Low-Temperature Furnace-Grown Reoxidized Nitrided Oxide Gate Dielectrics as a Barrier to Boron Penetration," IEEE Electron Device Letters, vol. 13, No. 4, Apr. 1992, pp. 217-219.
Chuan Lin et al, "Leakage Current, Reliability Characteristics, and Boron Penetration of Ultra-Thin (32-36.ANG.) O.sub.2 -Oxides and N.sub.2 O/NO Oxynitrides," International Electron Devices Meeting Technical Digest, Dec. 8-11, 1996, San Francisco, CA, pp. 331-334.
E. Hasegawa et al, "The Impact of Nitrogen Profile Engineering On Ultra-Thin Nitrided Oxide Films for Dual-Gate CMOS ULSI," International Electron Devices Meeting Technical Digest, Dec. 10-13, 1995, Washington, DC, pp. 327-330.
S. V. Hattangady, H. Niimi, and G. Lucovsky, "Controlled Nitrogen Incorporation at the Gate Oxide Surface," Applied Physics Letters, vol. 66, No. 25, Jun. 19, 1995, pp. 3495-3497.
Stanley Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration, Lattice Press, Sunset Beach, CA, 1990, pp. 124-131. Month Unknown.
T. Kuroi et al., "Novel NICE (Nitrogen Implantation into CMOS Gate Electrode and Source-Drain) Structure for High Reliability and High Performance 0.25 .mu.m Dual gate CMOS," International Electron Devices Meeting Technical Digest, Dec. 5-8, 1993, Washington, D.C., pp. 325-328.
Stanley Wolf, Silicon Processing for the VLSI Era, vol. 3: The Submicron MOSFET, Latttice Press, Sunset Beach, CA, 1995, pp. 305-313, 496-504, and 648-661. Month Unknown.
H. Sayama et al, "Low Voltage of Sub-Quarter Micron W-Polycide Dual Gate CMOS with Non-Uniformly Doped Channel," International Electron Devices Meeting Technical Digest, Dec. 8-11, 1996, San Francisco, CA, pp. 583-586.
Hattangady et al., "Ultrathin Nitrogen-Profile Engineered Gate Dielectric Films," International Electron Devices Meeting 1996, Dec. 8-11, 1996, San Francisco, CA, pp. 495-498.
C. T. Liu et al, "High Performance 0.2 .mu.m CMOS with 25 .ANG. Gate Oxide Grown on Nitrogen Implanted Si Subsstrates," International Electron Devices Meeting Technical Digest, San Francisco, CA, Dec. 8-11, 1996, pp. 499-502.
C.T. Liu et al., "25 .ANG. Gate Oxide without Boron Penetration for 0.25 and 0.3.mu.m PMOSFETs," 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 18-19. Month Unknown.
Dawson Robert
Fulford Jr. H. Jim
Gardner Mark I.
Hause Frederick N.
Michael Mark W.
Advanced Micro Devices , Inc.
Lebentritt Michael S.
Niebling John F.
LandOfFree
Ion implantation into a gate electrode layer using an implant pr does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ion implantation into a gate electrode layer using an implant pr, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ion implantation into a gate electrode layer using an implant pr will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1783797