Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-02-25
1999-12-21
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438424, 438526, 438527, 438529, 438530, 148DIG50, H01L 2176
Patent
active
060048646
ABSTRACT:
A method is described for forming trench isolation for integrated circuits on silicon wafers by selectively doping the trench regions by ion implantation and then etching these areas with a wet chemical etch. A dopant such as boron, is implanted in a sequence of energies and doses to provide a desired trench profile of heavily doped silicon. The implanted silicon etches far more rapidly than the surrounding silicon and is readily etched out forming a trench. The concentration of dopant diminishes rapidly in the periphery of the implanted region. As the etch front approaches the periphery, the silicon etch rate, likewise diminishes and the etch can be quenched to leave a uniform surface layer of enhanced boron concentration which lines the resultant trench to form an effective channel stop. Wet etched trenches provide advantages over trenches formed by RIE including smooth rounded trench profiles which reduce stress. In addition, trenches having widths below 0.25 microns and essentially vertical walls can readily be formed.
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Chen Chia-Hsiang
Chuang Kuo-Sheng
Huang Ji-Chung
Tseng Han-Liang
Ackerman Stephen B.
Dang Trung
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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