Inversion of scan clock for scan cells

Details Inversion of scan clock for scan cells Inversion of scan clock for scan cells

2008-10-29

2009-11-03

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000, C714S731000

Reexamination Certificate

active

07613967

ABSTRACT:
A device includes a scan circuit including a scan chain. The scan chain includes a first plurality of scan cells that receive a first scan clock signal in a first clock domain. A second plurality of scan cells receives a second scan clock signal in a second clock domain. A scan clock source generates the first scan clock signal and the second scan clock signal, and selectively inverts the first scan clock signal and the second scan clock signal based on an operating mode of the first plurality of scan cells and the second plurality of scan cells, respective flip-flop arrangements of the first clock domain and the second clock domain.

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