Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2004-07-29
2008-11-04
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S731000
Reexamination Certificate
active
07447961
ABSTRACT:
In one embodiment, an apparatus comprises a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain. A scan clock source, coupled to the scan chain, generates a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells. The first and the second clock signals have an inverted relationship.
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Louis-Jacques Jacques
Marvell International Ltd.
Tabone, Jr. John J.
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