Intra-decoder component block messaging

Details Intra-decoder component block messaging Intra-decoder component block messaging

2006-03-28

2006-03-28

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S756000, C714S785000

Reexamination Certificate

active

07020826

ABSTRACT:
A decoder and decoding method are described, in which a syndrome is calculated from a codeword in a syndrome generator, an error polynomial is generated based upon the syndrome in an error polynomial generator, an error location is determined from the error polynomial in the error location generator, an error magnitude is calculated from the error polynomial in the error magnitude generator and the codeword is corrected by a error corrected codeword generator responsive to location and error magnitude. An intra-decoder block messaging scheme is described in which one or more components generate inactivity messages to signal an ability to process data corresponding to a next codeword. A dual Chien search block implementation is described in which Chien block is used to determine the number of errors corresponding to a specified codeword, separately from error location and magnitude calculations performed by the Chien/Forney block. An enhanced Chien search cell architecture is described which utilizes an additional Galois field adder to synchronize the codeword and error vector, thereby decreasing delay and expense corresponding to an error correcting block implemented with a LIFO register.

REFERENCES:
patent: 4875211 (1989-10-01), Murai et al.
patent: 5099482 (1992-03-01), Cameron
patent: 5373511 (1994-12-01), Veksler
patent: 5712861 (1998-01-01), Inoue et al.
patent: 5905740 (1999-05-01), Williamson
patent: 6058500 (2000-05-01), DesJardins et al.
patent: 6061826 (2000-05-01), Thirumoorthy et al.
patent: 6065149 (2000-05-01), Yamanaka
patent: 6175945 (2001-01-01), Okita
patent: 6195781 (2001-02-01), Kosuge
patent: 6345376 (2002-02-01), Cox et al.
patent: 6347389 (2002-02-01), Boyer
patent: 6374383 (2002-04-01), Weng
patent: 6415413 (2002-07-01), Pan et al.
patent: 6487692 (2002-11-01), Morelos-Zaragoza
patent: 6735737 (2004-05-01), Sankaran et al.
patent: 0509430 (1992-10-01), None
patent: 0660535 (1995-06-01), None
PCT Search Report dated: Apr. 15, 2003.
“Quantum Reed—Solomon Codes”, Markus Grassl, Willi Geiselmann, and Thomas Beth, Institut für Algorithmen und Kognitive Systeme, Arbeitsgruppe Quantum Computing, Universität Karlsruhe, Am Fasanengarten 5, 76 128 Karlsruhe, Germany, pp. 1-14.
“Optimal Finite Field Multipliers for FPGAs”, Captain Gregory C. Ahlquist, Brent Nelson, and Michael Rice, article found at http://splish.ee.byu.edu/docs/ffmult.fp199.pdf—Similar pp., Mar. 1, 2001, 10 pages.
“Tutorial on Reed-Solomon Error Correction Coding”, William A. Geisel, NASA Technical Memorandum 102162, Aug. 1990, pp. 72-74.
“Error Control Systems for Digital Communication and Storage”, Stephen B. Wicker, Library of Congress Cataloging-in-Publication Data, p. 209.
“Parallel Decoder for Cellular Automata Based Byte Error Correcting Code”, S. Chattopadhyay and P. Pal Chaudhuri, 10th International Conference on VLSI Design, Jan. 1997, pp. 527-528.
“Designing a Reed-Solomon Codec in an ADSL System using a C6201 DSP”, by Han Kuo, article found, at http://www.csdmag.com
ews/des0111011.htm, Mar. 9, 2001, 10 pages.
“A Faster Way To Run Reed Solomon Decoders”, Torjell Berg and Aaron Brennan, American Microsystems Inc., Article found at http://www.eetasia.com/article—content.php3?article—id=8800067078 Mar. 9, 2001; posted: Jan. 1, 2001, 3 pages.
“XF-RSDEC Reed Solomon Decoder”, article found at http://www.xilinx.com/products/logicore/alliance/memec/xf—rsdec.pdf, Jan. 10, 2000, pp. 3-1-3-5.
“Reed-Solomon Codes—‘An introduction to Reed-Solomon codes: principles, architecture and implementation’”, article found at http://www.4i2i.com/reed—solomon—codes.htm, Mar. 9, 2001, 8 pages.
“Reed Solomon Decoder: TMS320C64x Implementation, ‘Digital Signal Processing Solutions’”, Jagadeesh Sankaran, Texas Instruments Application Report SPRA686—Dec. 2000, pp. 1-20, 31, 38, 49, 60, 67-70.
Iwaki, et al., Architecture of a High Speed Reed-Solomon Decoder, 8087 IEEE Transaction on Consumer Electronics, XP000441786, Jan. 14, 1994, pp. 75-81.
Kamada, et al., An Area Effective Standard Cell Based Channel Decoder LSI for Digital Satellite TV Broadcasting, XP-002349513, 1996, IEEE, pp. 337-346.
Tehranchi, et al., Reliability Estimates for Data Recovered from Compact Discs, Applied Optics, vol. 37, No. 2, Jan. 10, 1988, pp. 386-395.

Affiliated with

Also associated with

Rating

Intra-decoder component block messaging does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Intra-decoder component block messaging, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Intra-decoder component block messaging will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3560010