Intializing memory cells within a dynamic memory array prior...

Details Intializing memory cells within a dynamic memory array prior... Intializing memory cells within a dynamic memory array prior...

2000-02-12

2001-08-28

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S149000, C365S226000

Reexamination Certificate

active

06282135

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to dynamic memory arrays incorporating a memory cell plate biased at a voltage near the bit line equilibration voltage.
2.Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). Frequently, the bit lines of such a dynamic memory array are equilibrated to a voltage near one-half of the power supply voltage (i.e., “V
DD
/2 equilibration”) and the cell plate for all the memory cells is biased also at the mid-VDD voltage level.
During power-up of an integrated circuit incorporating a such a dynamic memory array, power-up circuitry frequently drives the voltage of the memory cell plate to its desired value. For example, for a circuit operating at a VDD of 2.5 volts, the memory cell plate may be driven during power-up to a typical voltage of 1.25 volts and maintained at that voltage. The true and complement bit lines of the memory array are equilibrated together, and also frequently equilibrated to the memory cell plate voltage.
During power-up, when the memory cell plate is driven from ground to its operating voltage of 1.25 volts, each of the internal memory cell nodes is capacitively coupled by the cell plate, and each internal node follows the cell plate and arrives at substantially the same voltage of 1.25 volts (for this example). At the same time, the true and complement bit lines may also be driven to 1.25 volts in preparation for the first internal memory operation. When the first internal memory operations occur, the voltage in each memory cell is substantially equal to the voltage of its associated bit line. Consequently, when the word line is driven high, there is no differential voltage developed between a true bit line and its complement bit line, and the associated bit line sense amplifier is strobed with substantially no signal. As is true with any latching circuit, a meta-stable condition may easily arise, during which the bit line sense amplifier cannot quickly determine which way to latch. When operated with fast cycle times, a memory array may not have enough time to wait for the meta-stable latches to eventually “decide” which way to latch. As a result of this indecision, the first write cycle to address a given word line may establish very poor voltage levels in memory cells of the given word line.
Initialization cycles are frequently performed after the power supply voltages are stable to ensure that peripheral circuits are “exercised” a few times to properly and accurately set the voltages of various nodes. Such cycles are, however, externally-controlled cycles which may presume correct operation of the bit lines and sense amplifiers. In circuits with delicate timing or other constraints, the possibility of such meta-stable operation, even during initialization cycles, may be extremely undesirable.
SUMMARY OF THE INVENTION
The present invention prevents the bit line sense amplifiers, during the first cycles after power-up, from having to sense memory cells “initialized” at a voltage near the bit line equilibration voltage. In an exemplary embodiment, all the memory cells are initialized to a low voltage under automatic internal control during power-up. Provision is made to force every word line simultaneously high, to force a common equilibrate node (to which the bit lines are normally equilibrated) to VSS (i.e., ground), and to ensure that any bit line equilibration and array select transistors are on. Since each sense amplifier is then coupled to a common node at VSS by precharge signals, each bit line (both true and complement) is driven to VSS and all memory cells are likewise forced to VSS, even if the word lines are no higher than a threshold voltage above VSS. At about the same time, the memory cell plate is established at a voltage near the eventual bit line equilibration voltage (for the exemplary embodiment, preferably around 1.0 volts) by other power-up circuits. Then, when normal cycles begin, the very first internal memory operation in the memory array occurs with memory array nodes (bit lines, cell plate) properly established, and all memory cells initialized at one of the two valid states (in this example, at VSS).
In a broader embodiment of the invention suitable for use in an integrated circuit having a dynamic memory array block, a method of operating the integrated circuit includes initializing, during an internally-controlled power-up sequence, all respective memory cells within the array block to a respective non-intermediate voltage before enabling, during an internal memory operation, bit line sense amplifiers associated with the array block, and then performing internal memory operations as a result of external memory cycle requests received by the integrated circuit.
For certain embodiments, each respective non-intermediate voltage is substantially different from a bit line equilibration voltage of the array block during normal operation after completion of the internally-controlled power-up sequence. Each respective non-intermediate voltage may be substantially equal to either a low restore voltage level or a high restore voltage level of the bit line sense amplifiers within the array block under normal operation, or may alternatively all be equal to the low restore voltage level.
The internally-controlled power-up sequence may include performing a plurality of internal memory operations to initialize node voltages within other internal circuits prior to performing internal memory operations as a result of external memory cycle requests received by the integrated circuit.
The initializing step may include forcing each true and complement bit line within the array block to a respective voltage substantially equal to either a low restore voltage level or a high restore voltage level of the bit line sense amplifiers within the array block during normal operation after completion of the internally-controlled power-up sequence, and forcing a word line within the array block to a suitable voltage to turn on the access transistor within each memory cell associated with the word line. Alternatively, a plurality of word lines within the array block may be forced simultaneously to a suitable voltage to turn on the access transistor within each memory cell associated with any of the plurality of word lines, or all the word lines within the array block may be simultaneously forced to a suitable voltage.
In a preferred embodiment, the initializing step includes forcing both the true and complement bit line of each complementary bit line pair within the array block to the restore low voltage level, and forcing each word line within the array block to a voltage above the threshold voltage of the access transistor within each memory cell within the array block. Each word line within the array block may be forced sequentially, in sequential groups, or all simultaneously to the voltage. If each bit line is coupled to an associated bit line sense amplifier through a transistor gated by an array select signal, any array select signal associated with the array block may be held active so that each bit line is actively coupled to an associated internal bit line sense amplifier node.
In some embodiments, both the true and complement bit line of each complementary bit line pair within the array block may be forced to the restore low voltage level by ensuring, if each bit line is coupled to a shared bit line equilibrate node through a transistor gated by an equilibrate signal, that any such equilibrate signal associated with the array block is held active so that each bit line is actively coupled to the shared bit line equilibrate node, and forcing the shared bit line equilibrate node to the restore low voltage level.
The step of forcing each wor

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