Interrupt controller and method of accessing interrupts

Details Interrupt controller and method of accessing interrupts Interrupt controller and method of accessing interrupts

2000-09-29

2004-05-25

Vo, Tim (Department: 2181)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S261000, C710S262000

Reexamination Certificate

active

06742065

ABSTRACT:

This application claims priority to Korean Patent Application No. 1999-42354, filed on Oct. 1, 1999, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to interrupt controllers for computer systems and, more particularly, to interrupt controllers for use in reduced instruction set computers (RISCs).
BACKGROUND OF THE INVENTION
Generally, computers utilizing microprocessors manufactured by Intel Corporation, such as the 8088, 8086, 80186, 80286, i386™, and i486™ also utilize Intel 8259 series programmable interrupt controllers. The 8259 series controllers are described in detail in “Microprocessor and Peripheral Handbook” published by Intel, pages 3-171, October 1988. An 8259 interrupt controller provides interrupt signals to a processor for handling various hardware devices associated with the processor. Other programmable controllers are disclosed, for example, in U.S. Pat. No. 5,481,725, entitled “METHOD FOR PROVIDING PROGRAMMABLE INTERRUPT FOR EMBEDDED HARDWARE USED WITH PROGRAMMABLE INTERRUPT CONTROLLERS” issued to Jayakumar et al. on Aug. 3, 1993, and in U.S. Pat. No. 5,603,035 entitled “PROGRAMMABLE INTERRUPT CONTROLER, INTERRUPT SYSTEM AND ITNERRUPT CONTROL PROCESS” issued to Erramoun et al. on May 27, 1994.
An interrupt accessing procedure is generally divided into two manners. One is “vectored interrupt”, wherein an interrupt controller informs a central processing unit (CPU) of a vector that is an intrinsic number of each interrupt source. The CPU processes an interrupt service routine corresponding to the vector sent from the interrupt controller, by jumping to a memory location containing the service routine. The other is “non-vectored interrupt”, wherein an interrupt controller informs a CPU of only the fact that an interrupt has occurred. In this case, an interrupt source and a location of an interrupt service routine corresponding to the interrupt source is determined by software.
In a reduced instruction set computer (RISC) such as the ARM CPU series produced by Advanced RISC Machines (ARM) Ltd. which supports non-vectored interrupts, when an interrupt occurs, an interrupt accessing procedure is performed as illustrated in FIG.
1
.
Referring to
FIG. 1
, which shows a conventional interrupt accessing procedure of an RISC system, when an interrupt controller
2
generates an interrupt signal INT, a CPU
1
acknowledges that and jumps to an exception vector table via arrow (a). The exception vector table is a nonvolatile memory and a branch instruction such as B ISR_
0
is stored therein by a programmer. According to the branch instruction BISR_
0
, the CPU
1
jumps to a routine ISR_
0
, via arrow (b), and checks which of interrupt sources is
0
, is
1
, . . . , and isn was the source that made the interrupt request. By executing the routine ISR_
0
, the CPU addresses the interrupt controller
2
, and then detects the interrupt request stored in an interrupt pending register therein. Thereafter, control flow jumps via arrow (c) to a position where an interrupt service routine for performing the interrupt request is located.
A problem of the RISCs supporting non-vectored interrupts described above is low interrupt handing speed because of the addressing step needed to detect the presence of the interrupt request. Therefore, a need exists for an interrupt controller and an interrupt handling method capable of improving the interrupt handling speed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an interrupt controller and an interrupt accessing method capable of reducing interrupt accessing time of RISCs that does not support vectored interrupts.
According to an aspect of the present invention, an interrupt controller comprises: first storing unit for storing an interrupt request of a plurality of interrupt sources; a priority determination unit, for determining a priority level of each of the interrupt sources and generating one or more indexes and one or more interrupt signals, in response to the interrupt request; a vector generator for generating one or more vectors in response to the indexes; second storing unit for storing the one or more vectors; an instruction generator for generating a branch instruction in response to the one or more vectors, and selecting either the generated branch instruction or a CPU instruction for outputting to a CPU; and a control logic for controlling overall operations of the interrupt controller.
According to another aspect of the present invention, there is a method of accessing interrupts in an RISC. The method comprises the steps of: checking whether an interrupt request is made by an embedded device; finding out a final interrupt source by determining a priority level of the interrupt source; generating a branch instruction corresponding to the determined priority level; generating an interrupt signal to a CPU; inputting the branch instruction to the CPU in response to the interrupt signal; and processing an interrupt service routine addressed by the branch instruction.


REFERENCES:
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patent: 4523277 (1985-06-01), Schnathorst
patent: 5701493 (1997-12-01), Jaggar
patent: 6070220 (2000-05-01), Katayama
patent: 6298410 (2001-10-01), Jayakumar et al.
patent: 1063588 (2000-12-01), None
patent: 2012082 (1979-07-01), None
patent: 10171665 (1998-06-01), None
Search Report of Great Britain Application No. GB 0023920.2.

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