Interposer chip and multi-chip package having the interposer...

Details Interposer chip and multi-chip package having the interposer... Interposer chip and multi-chip package having the interposer...

2011-04-19

2011-04-19

Tran, Tan N (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S260000, C257SE23002

Reexamination Certificate

active

07928435

ABSTRACT:
An interposer chip may include an insulating substrate, conductive patterns, and a test pattern. The conductive patterns may be formed on the insulating substrate. Further, the conductive patterns may be electrically connected to conductive wires. The test pattern may be connected to the conductive patterns. A test current for testing an electrical connection between the conductive patterns and the conductive wires may flow through the test pattern. Thus, the interposer chip may have the test pattern connected to the conductive patterns, so that the test current may flow to the test pattern through the conductive wires and the conductive patterns. As a result, an electrical connection between the conductive wires and the conductive patterns may be identified based on the test current supplied to the test pattern.

REFERENCES:
patent: 4951098 (1990-08-01), Albergo et al.
patent: 2004/0245651 (2004-12-01), Nishisako et al.
patent: 2006/0131718 (2006-06-01), Tao et al.
patent: 2007-103411 (2007-04-01), None
patent: 10-2006-0074796 (2006-07-01), None
patent: 10-0723518 (2007-05-01), None

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