Interposer and stacked chip package

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip

Reexamination Certificate

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Details

C257S685000, C257S686000, C257S723000, C257S773000, C257S778000, C257S786000, C257SE23015, C257SE23020, C257SE27137, C257SE23144, C257SE27161, C257SE25006, C257SE25013, C257SE25021, C257SE25027, C257SE23085

Reexamination Certificate

active

07663245

ABSTRACT:
An interposer may include a base substrate supporting an array of conductive lands. The conductive land may have an identical shape and size. The conductive lands may be provided at regular intervals on the base substrate. The conductive land pitch may be determined such that adjacent conductive lands may be electrically connected by one end of an electric connection member. Alternatively, each conductive land may provide respective bonding locations to which ends of two different electric connection members may be bonded. A stacked chip package may include an interposer that may be fabricated by cutting an interposer to size. In the stacked chip package, electrical connections may be made through the interposer between an upper semiconductor chip and a package substrate, between the upper semiconductor chip and a lower semiconductor chip, and/or between the lower semiconductor chip and the package substrate.

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patent: 6008534 (1999-12-01), Fulcher
patent: 6137168 (2000-10-01), Kirkman
patent: 6664625 (2003-12-01), Hiruma
patent: 7057292 (2006-06-01), Elenius et al.
patent: 7291900 (2007-11-01), Corisis et al.
patent: 4-28253 (1992-01-01), None
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patent: 2001-007278 (2001-01-01), None
patent: 2004-235352 (2004-08-01), None
patent: 1020010062929 (2001-07-01), None

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