Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-08-09
2004-01-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06675338
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of microchip design. More specifically, the present invention relates to the use of internally generated vectors for the burnin system for testing a microchip.
2. The Background
When constructing a microchip, it is typical to run what is called a “burn-in” test on the circuits in the chip. Burn-in is a long, thorough, carefully controlled preliminary test performed in order to stabilize a chip's electrical characteristics after manufacture and to ensure that it will function according to rated specifications. For microchips, a commonly run burn-in test is to run the chip at a high temperature for an extended period of time (such as 48 hours).
Microchips are often designed with test circuitry built-into the chip for use in the test phase of development. The circuitry not be used after shipment of the chip to customers, but the built-in circuitry allows tests to be performed by test facilities at a high rate of speed. A common test design is called a full scan design, which gives observability and controllability over internal states of the microchip to whoever is running the tests. When this capability is used along with the high temperature test, this allows every state of every flip-flop in the circuit to be tested at the high temperature, and oftentimes will reveal a problem in design or manufacture that no other test uncovered.
The goal in designing good test circuitry in this area, therefore, is to be able to toggle as many internal nodes of the microchip as possible during the burn-in stage in order to make the whole chip function during testing, which provides the maximum amount of stress testing of the microchip. This has generally been accomplished by designing the test circuitry to utilize automatic test pattern generation (ATPG) vectors generated by a software tool accompanying the microchip. The ATPG vectors are loaded into a memory, and then sequentially fed to the microchip in order to test all the possible states of the flip-flops in the circuit during burnin.
There is limited memory, however, available in the burnin system. Adding external memory adds additional costs to the burnin process. What is needed is an efficient solution which allows for better toggle coverage while still utilizing the limited memory available.
SUMMARY OF THE INVENTION
Internally generating test vectors on a microchip during a burnin stage allows for better toggle coverage while not requiring external memory. A test access port a (TAP) controller which accepts signals from a user and indicates to a linear feedback shift register (LFSR) that the microchip is in the burnin stage. The LFSR then may generate a set of pseudorandom values using a polynomial. The values are then shifted one per clock cycle into the internal scan chain of flips-flops on the chip, which toggles the internal states of the chip. New pseudorandom values are also generated one-by-one during the shift. By using this approach, the internal states of the chip are toggle without the use of an external memory for the burnin system.
REFERENCES:
patent: 4713605 (1987-12-01), Iyer et al.
patent: 5136705 (1992-08-01), Stubbs et al.
patent: 5367685 (1994-11-01), Gosling
patent: 5570375 (1996-10-01), Tsai et al.
patent: 5604756 (1997-02-01), Kawata
patent: 5615137 (1997-03-01), Holzmann et al.
patent: 5748964 (1998-05-01), Gosling
patent: 5809036 (1998-09-01), Champlin
patent: 5825785 (1998-10-01), Barry et al.
patent: 6006345 (1999-12-01), Berry, Jr.
patent: 6367044 (2002-04-01), Komoike
patent: 6370665 (2002-04-01), Noguchi
patent: 6415409 (2002-07-01), Rhodes et al.
patent: 0 685 792 (1995-05-01), None
patent: WO 98/19237 (1998-05-01), None
David Basin “Java Bytecode Verification by Model Checking” System Abstract, pp. 492-495 IT-Research Security (TZ/FE34).
Britt Cynthia
De'cady Albert
Hanish Marc S.
Thelen Reid & Priest LLP
LandOfFree
Internally generated vectors for burnin system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Internally generated vectors for burnin system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Internally generated vectors for burnin system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3220841