Internal synchronous static RAM

Details Internal synchronous static RAM Internal synchronous static RAM

1990-05-09

1991-09-10

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Precharge

365233, 3652335, 36518908, 365191, G11C 700, G11C 114

Patent

active

050479849

ABSTRACT:
An internal synchronous SRAM comprises an SRAM cell array having a number of SRAM cells arranged in the form of a matrix, a precharge circuit connected to all bit lines of the SRAM cell array for precharging the bit lines in response to a bit line precharge signal, a selector connected to all the bit lines and responding to a bit line select signal for connecting only a selected pair of bit lines to a pair of common data lines, a pull-down circuit connected to the pair of common data lines and for pulling down the common data lines in response to a pull-down control signal and a sense amplifier connected to the common data lines for amplifying a data signal appearing on the common data lines. In addition, an address transition detector is connected to receive an address signal for generating an internal synchronous signal in response to transition of the address signal, and a control pulse generator is connected to receive the internal synchronous signal and operating to generate the pull-down control signal and the bit line precharge signal in response to the internal synchronous signal.

REFERENCES:
patent: 4751683 (1988-06-01), Wada et al.

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