Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge
Reexamination Certificate
1999-12-09
2001-10-09
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Accelerating charge or discharge
C365S185250, C365S185330
Reexamination Certificate
active
06301177
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to flash memory devices, and more particularly to circuits for discharging negative high voltages after an erase operation.
BACKGROUND OF THE INVENTION
A typical construction of a cell (or cell transistor) of a flash memory is shown in FIG.
1
. This cell can be used for multi-bit storage. A source
3
and a drain
4
, each being formed of an N+ diffused region in a P+ semiconductor substrate
2
, are separated from each other through a channel region
5
, which is also defined in the substrate
2
. A thin insulating film
7
, which is under 100 Å, is then formed over the channel region
5
, and a floating gate
6
is then formed over the thin insulating film
7
. A second insulating film
9
, such as an O-N-O (Oxide-Nitride-Oxide) film, is formed over the floating gate
6
and a control gate
8
is then formed over the second insulating film
9
. The second insulating film
9
acts to isolate a control gate
8
from the floating gate
6
. The source
3
, drain
4
, control gate
8
, and substrate
2
are each connected to corresponding voltage sources V
s
(the drain voltage), V
d
(the source voltage), V
g
(the gate voltage), and V
b
(the bulk voltage), respectively for programming, erasing, and reading operations.
In programming, as is well known, a selected memory cell is programmed by means of a hot electron injection between the channel region
5
and the floating gate
6
. In this case, the source
3
and substrate
2
are held at a ground voltage, a high voltage (e.g., V
g
=10V) is applied to the control gate
8
, and a voltage sufficient to induce the hot electrons therein (e.g., 5V through 6V) is provided to the drain
4
. After it is programmed, a threshold voltage of the selected memory cell is increased by the deposition of electrons.
To read data from the programmed cell, a voltage of about 1V is applied to the drain
4
, a power source voltage (about 4.5V) is applied to the control gate
8
, and the source
3
is held to the ground voltage. Since the increased threshold voltage of the programmed memory cell acts as a blocking potential even upon the gate voltage during a read-out operation, the programmed cell is considered to be an off-cell, which has a threshold voltage between 6V and 7V.
Erasing a memory cell is accomplished by conducting an F-N (Fowler-Nordheim) tunneling effect, in which the control gate
8
is coupled to a high negative voltage of about −10V, and the substrate
2
(or bulk) is coupled to a positive voltage of about 5V. This acts to induce the tunneling between the substrate
2
and the control gate
8
. While doing this, the drain
4
is conditioned to a high impedance state (i.e., a floating state). A strong electric field, induced by the voltage bias conditions is applied between the control gate
8
and a bulk region (i.e., the substrate
2
), and causes the electrons to move into the source
3
. The F-N tunneling normally occurs when an electric field of 6~7MV/cm is developed between the floating gate
6
and the substrate
2
, which are separated by the thin insulating film
7
having a thickness of under 100 Å. The erased cell has a lower threshold voltage than before, and is thereby sensed as an on-cell, which has a threshold voltage between 1~3V.
In a usual architecture of a memory cell array in a flash memory, the bulk region (or the substrate
2
) combines active regions of memory cells, so that memory cells formed in the same bulk region are spontaneously erased at the same time. Therefore, units of erasing (hereinafter referred to as “sectors”, e.g., one sector of 64K) are determined in accordance with the number of separate bulk regions. Table 1 shows levels of the voltages used in programming, erasing, and reading.
TABLE 1
operation mode
V
g
V
d
V
s
V
b
programming
10
V
5 ~ 6 V
0 V
0 V
erasing
−10
V
floating
floating
5 V
reading
4.5
V
1 V
0 V
0 V
erase repairing
3
V
5 ~ 6 V
0 V
0 V
Once an erase operation for memory cells is performed, memory cells whose threshold voltages are under 0V, among the memory cells, are erased. The threshold voltages of these memory cells are positioned at an range of uniform distribution. The memory cells with threshold voltages of 0V, are referred to as over-erased cells that have to be cured by a repairing operation (i.e., erase repairing) in order to have threshold voltages set higher than 0V.
In a general erase repairing operation, the source
3
and substrate
2
of the over-erased memory cell are grounded, the control gate
8
is connected to a positive voltage of about 3V that is lower than a program voltage (e.g., 10V), and the drain
4
is connected to a positive voltage of about 5V through 6V. As a result of this, negative charges smaller than those in the programming operation are gathered in the floating gate electrode
6
and so the negative potential formed at the gate electrode causes the threshold voltage of the memory cell to be increased over 0V (or the ground voltage).
During an erase operation, as shown in Table 1, word lines coupled to control gates
8
of all of the memory cells belonging to a selected sector should be charged to a negative voltage. However, for performing a verifying operation and another programming and reading after the erase cycle, the word lines that have been charged to a negative voltage must first be discharged to 0V (or the ground voltage) from these higher negative voltages. While the negative voltage about −10V at the word line is being brought back to 0V, a high electric field may appear between the gate electrode and the source
3
or the drain
4
, which may destroy an oxide layer (i.e., the thin insulating layer
7
) between the floating gate
6
and a surface of the substrate
2
. Alternately, this may induce a breakdown between a bulk (i.e., the substrate
2
) and a junction in the memory cell transistor.
SUMMARY OF THE INVENTION
The present invention is intended to solve the problems. And, it is an object of the invention to provide a circuit of a non-volatile flash memory device for preventing a destruction of a gate oxide layer and physical damages in a memory cell transistor when a negative high voltage is being discharged after an erase operation.
In order to accomplish those objects, a memory device includes an output node having a negative voltage, a first discharging unit, being connected to the output node, for discharging the negative voltage in response to a first signal and a second signal, a second discharging unit, being connected to the output node, for discharging the negative voltage in response to the second signal and a third signal, and a third discharging unit, being connected to the output node, for discharging the negative voltage in response to a fourth signal and a fifth signal.
Another feature of a memory device includes a node of a negative voltage, a first discharging unit, being connected to the node, for discharging the negative voltage in response to a first signal and a second signal, when the negative voltage is a first voltage level, a second discharging unit, being connected to the node, for discharging the negative voltage in response to the second signal and a third signal, when the negative voltage is a second voltage level, and a third discharging unit, being connected to the node, for discharging the negative voltage in response to a fourth signal and a fifth signal, when the negative voltage is a third voltage level.
REFERENCES:
patent: 5361185 (1994-11-01), Yu
patent: 5511022 (1996-04-01), Yin et al.
patent: 6031774 (2000-02-01), Chung
Jones Volentine, L.L.C.
Lam David
Nelms David
Samsung Electronics Co,. Ltd.
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