Internal clock signal generator including circuit for...

Details Internal clock signal generator including circuit for... Internal clock signal generator including circuit for...

1998-10-08

2002-04-16

Vo, Don N. (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S147000

Reexamination Certificate

active

06373913

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to clock signal generators suitable for use in an integrated circuit memory device. More particularly, the present invention relates to an internal clock signal generator for synchronizing an internal clock with an external clock signal.
BACKGROUND OF THE INVENTION
Integrated circuit devices such as an integrated circuit memory or central processing units, which operate in synchronization with an external clock signal, typically generate an internal clock signal using a clock buffer and a clock driver. As a result, the internal clock signal may be delayed compared to the external clock signal. Such a delay may cause deterioration in the performance of the device during high frequency operation. In particular, at high frequencies of operation, the access time t
ac
(i.e., the time required for outputting data after an external clock signal is input) may become longer than the time required for generating an internal clock signal from the received external clock signal. Deterioration of the performance of a semiconductor device at higher frequencies may be reduced by synchronizing the internal clock signal with the external clock signal. Conventionally, this synchronization may be accomplished with a delay locked loop (DLL) or a phase locked loop (PLL) which are used as the internal clock signal generator.
FIG. 1
is a schematic diagram of a conventional DLL. As seen in
FIG. 1
, the DLL includes a phase detector
1
, a low pass filter (LFF)
2
, and a voltage control delay line
3
. The phase detector
1
compares the phases of an external clock signal Ext.CLK and an internal clock signal Int.CLK and detects the difference between the phases. The LPF
2
is connected to the output of the phase detector
1
and generates a control voltage v
cont
for controlling the delay time of the voltage control delay line
3
. The voltage control delay line
3
typically includes a plurality of inverters which are serially connected and outputs the internal clock signal Int.CLK by delaying the external clock signal by a predetermined time specified by the voltage control input. Unfortunately, however, synchronizing the internal clock signal with the external clock signal may take hundreds of cycles of the external clock signal. Furthermore, the DLL circuit may require several tens of milliamps of current during operation. Therefore, it may be difficult to utilize the DLL in an integrated circuit device.
FIG. 2
is a schematic diagram of a conventional PLL. As seen in
FIG. 2
, the PLL includes a phase-frequency detector
11
, a LPF
12
, and a voltage control delay line
13
. The phase-frequency detector
11
compares the phases and frequencies of the external clock signal Ext.CLK and the internal clock signal Int.CLK, and detects the differences in phases and frequencies. The LPF
12
is connected to the output of the phase detector
11
and generates a control voltage v
cont
for controlling the delay time of the voltage control delay line
13
. The voltage control delay line
13
outputs the internal clock signal Int.CLK in response to the control voltage v
cont
and the internal clock signal Int.CLK which is fed back to the input of the voltage control delay line
13
. Thus, the voltage control delay line
13
acts as a ring oscillator.
The PLL of
FIG. 2
, however, may have the same problems as the DLL of FIG.
1
. Recently, the PLL and the DLL have been coupled together to utilize the quick locking time of the PLL and the wide locking range of the DLL. However, this combination may not solve all of the problems with the DLL and the PLL.
As a result of the shortcomings of the PLL and the DLL, a synchronized delay circuit has been suggested which uses simple delay means to match the phase of the internal clock signal with the phase of the external clock signal. This phase matching may be accomplished by making the delay time of the internal clock signal an integer multiple of the period of the external clock signal. In such a system, a synchronous delay line (SDL), a synchronous mirror delay (SMD), and a hierarchical phase lock delay (HPLD) may be utilized as the synchronized delay circuit.
FIG. 3
is a schematic diagram of a conventional synchronous delay circuit. As seen in
FIG. 3
, the synchronous delay line includes a clock buffer
21
, a dummy clock delay
22
, a first clock delay portion
23
, a comparing portion
24
, a second clock delay portion
25
, and a clock driver
26
. In the circuit of
FIG. 3
, the clock buffer
21
receives an external clock signal Ext.CLK and outputs a first clock signal CLK
1
in which the external clock signal is delayed by a first delay time d1. As is further seen in
FIG. 3
, tCK represents the period of the external clock signal. The dummy clock delay
22
controls the phase difference between the external clock signal and internal clock signal Int.CLK such that the phase difference is an integer multiple of the period tCK. The dummy clock delay
22
delays the first clock signal CLK
1
by the sum of the first delay time d1 and a second delay time d2 to provide a second clock signal CLK
2
.
The first clock delay portion
23
includes first unit delays
27
which are serially connected and which output a third clock signal CLK
3
. The output CLK
3
is a delayed version of the second clock signal CLK
2
and may be delayed by different times. The comparing portion
24
includes a plurality of comparators
28
which compare the first clock signal CLK
1
with the third clock signal CLK
3
delayed by the period tCK from the first clock signal CLK
1
. Thus, a fourth clock signal is delayed by the difference between the period tCK and the sum of the first and second delay times d1 and d2 compared with the second clock signal CLK
2
.
The second clock delay portion
25
includes second unit delays
29
which are connected in series and output a fifth clock signal CLK
5
by delaying the first clock signal CLK
1
by the difference between the period tCK and the sum of the first and second delay times d1 and d2. The clock driver
26
outputs the internal clock signal Int.CLK delayed by the second delay time d2 by receiving the fifth clock signal CLK
5
.
FIG. 4
is a timing diagram illustrating the operational state of the synchronous delay line of FIG.
3
. As seen in
FIG. 4
, the first clock signal CLK
1
is delayed by a first time d1 when compared with the external clock signal Ext.CLK. The second clock signal CLK
2
is delayed by the sum of the first delay time d1 and a second delay time d2 compared with the first clock signal CLK
1
. The third clock signal CLK
3
is the second clock signal CLK
2
delayed by an integer multiple of the delay time of the first unit delay
27
. The fourth clock signal CLK
4
is one of the third clock signal CLK
3
which was delayed by an integer multiple of the period tCK of the external clock Ext.CLK. In the embodiment illustrated in
FIG. 3
, the fourth clock signal CLK
4
corresponds to the clock signal CLK
1
delayed by one period of the external clock signal.
The fifth clock signal CLK
5
corresponds to the fourth clock signal CLK
4
delayed by the difference tCK minus (d1+d2) between the period tCK of the external clock signal Ext.CLK and the sum of the first delay time d1 and the second delay time d2. The Internal clock signal Int.CLK then corresponds to the fifth clock signal CLK
5
delayed by the second delay time d2. Thus, the internal clock signal Int.CLK is delayed from the external clock signal Ext.CLK by twice the period tCK of the external clock signal. Thus, the internal clock signal Int.CLK is synchronized with the external clock signal Ext.CLK.
The conventional SDL circuit described above is an open loop circuit unlike the PLL and DLL circuits which are closed loop circuits. Thus, the locking time of the SDL circuit is an integer multiple of the period tCK of the external clock signal. Accordingly, the locking time of the SDL circuit may be shorter than the locking time of the PLL and DLL circuits. However, the degree of locking accuracy of the SD

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