Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-02-22
2003-03-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100, C365S230060
Reexamination Certificate
active
06529423
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and more particularly, to an internal clock signal delay circuit for a synchronous DRAM.
2. Description of the Related Art
A synchronous DRAM operates in synchronization with an internal clock signal generated in response to an external clock signal from a CPU. In reading a first data from a row of memory cells of a synchronous DRAM, a row address strobe (RAS) signal enables a reading wordline, and then column select line (CSL) is enabled. Generally, the first data from a row requires more time between enabling the wordlines and selecting the column lines for data output. However, when the clock frequency of the CPU is high, that is, when the period of a clock signal is short, the synchronous DRAM may need to delay the CSL enabling signal by more than one clock period, so that the first data is valid when read.
SUMMARY OF THE INVENTION
The present invention is directed to a synchronous DRAM in which internal clock signal is delayed in three CAS latency modes to control the timing of CSL enabling.
In accordance with an embodiment of the present invention, a semiconductor device includes a CAS latency signal generator that generates CAS latency signals comprising a first CAS latency signal, a second CAS latency signal and a third CAS latency signal, and an internal clock delay circuit that receives one of the CAS latency signals and an internal clock signal and delays the internal clock signal by a predetermined time in response to the received CAS latency signal. The internal clock delay circuit includes delay circuits that delays the internal clock signal, and the internal clock signal passes through only one among the delayers when the semiconductor device operates in the second CAS latency mode.
Another embodiment of the invention provides a semiconductor device, which includes: a CAS latency signal generator that generates CAS latency signals; and an internal clock delay circuit that receives an internal clock signal and second and third CAS latency signals and generates a delayed internal clock signal. The second and third CAS latency signals are disabled when the semiconductor device operates in a first CAS latency mode, the second CAS latency signal is enabled when the semiconductor device operates in a second CAS latency mode, and the third CAS latency signal is enabled when the semiconductor device operates in a third CAS latency mode. The internal clock delay circuit includes: a first delay circuit that receives the internal clock signal; a second delay circuit connected to the first delay circuit; a third delay circuit connected to the second delay circuit; a first controller that receives an output signal of the first delay circuit and the second CAS latency signal; a second controller that receives an output signal of the second delay circuit and the second and third CAS latency signals; and a third controller that receives an output signal of the third delay circuit and the second and third CAS latency signals. The internal clock delay circuit can further include a fourth controller that receives outputs of the first, second and third controllers.
Still another embodiment of the invention provides a semiconductor device, which includes: a CAS latency signal generator that generates CAS latency signals; and an internal clock delay circuit that receives an internal clock signal and first and third CAS latency signals and generates a delayed internal clock signal. The first CAS latency signal is enabled when the semiconductor device operates in a first CAS latency mode, the first and third CAS latency signals are disabled when the semiconductor device operates in a second CAS latency mode, and the third CAS latency signal is enabled when the semiconductor device operates in a third CAS latency mode. The internal clock delay circuit includes: a first delay circuit that receives the internal clock signal; a second delay circuit connected to the first delay circuit; a third delay circuit connected to the first delay circuit in parallel with the second delay circuit; a first controller that receives an output signal of the first delay circuit and the first and third CAS latency signals; a second controller that receives an output signal of the second delay circuit and the first CAS latency signal; and a third controller that receives an output signal of the third delay circuit and the third CAS latency signal. The internal clock delay circuit can further include a fourth controller that receives the outputs of the first, second and third controllers.
The present invention is also directed to a method for delaying the internal clock signal of a synchronous DRAM, which decreases the generation time of the delayed internal clock signal in the second CAS latency mode. The method includes: inputting an internal clock signal to an internal clock delay circuit, which includes delay circuits, of a semiconductor device; and inputting CAS latency signals to the internal clock delay circuit to determine CAS latency modes of the semiconductor device; and outputting the internal clock signal through the delayers as an output signal of the internal clock signal delay circuit. The internal clock signal passes through one of the delay circuits in a second CAS latency mode and passes through at least two delay circuits among the delay circuits in either a first CAS latency mode or a third CAS latency mode.
REFERENCES:
patent: 5444398 (1995-08-01), Kiehl et al.
patent: 5444667 (1995-08-01), Obara
patent: 5566108 (1996-10-01), Kitamura
patent: 5729500 (1998-03-01), Shinozaki
patent: 6151270 (2000-11-01), Jeong
Hong Sang-pyo
Yoon Sei-seung
Heid David W.
Le Thong
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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