Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-09-28
1996-09-24
Hudspeth, David R.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 21, 326121, H03K 1901
Patent
active
055594530
ABSTRACT:
A low power, high speed, multistage asynchronous logic circuit having an interlocked restore mechanism. A first logic circuit detects a valid input signal and drives an output to a second logic circuit. The second logic circuit receives inputs from the first logic circuit and drives a data ready signal back to the first logic circuit when it detects the output from the first logic circuit. The first logic circuit resets when it receives the data ready signal from the second logic circuit and it detects that its inputs have been reset.
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Covino James J.
Sousa Jose R.
Hudspeth David R.
International Business Machines - Corporation
Walter Howard J.
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