Interleaving architecture and method for a high density FIFO

Details Interleaving architecture and method for a high density FIFO Interleaving architecture and method for a high density FIFO

1995-12-29

1997-09-02

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518904, G11C 1300

Patent

active

056639104

ABSTRACT:
A plurality of parallel single port memory arrays are coupled between a corresponding plurality of input FIFO sets and a corresponding plurality of output FIFO sets to create a high-speed FIFO memory device. The input FIFO sets, which provide data values to their corresponding single port memory arrays, are responsive to a write clock signal. The output FIFO sets, which receive data values from their corresponding single port memory arrays, are responsive to a read clock signal. The order of read and write operations within each single port memory array is controlled by a corresponding state machine which is coupled to either the write clock signal or the read clock signal. Each of the parallel single port memory arrays operates independently. The input FIFO sets de-interleave an input data stream into a plurality of intermediate data streams. Each intermediate data stream is routed through a single port memory array to an output FIFO set. The intermediate data streams are interleaved and transmitted to an output port. In one embodiment, the high-speed FIFO memory device has the capability to retransmit previously transmitted information.

REFERENCES:
patent: 5596533 (1997-01-01), Park

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