Interleaving apparatus and method for a communication system

Details Interleaving apparatus and method for a communication system Interleaving apparatus and method for a communication system

2005-06-21

2005-06-21

Anderson, Matthew D. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

Reexamination Certificate

active

06910110

ABSTRACT:
An interleaving apparatus and method for a communication system which can be applied to determine a new interleaver size N′=2m×(j+1) and addresses of0to N′−1, if a given interleaver size N is larger than 2m×j and smaller than 2m×(j+1), where m represents a first parameter indicating a number of consecutive zero bits from a least significant bit (LSB) to a most significant bit (MSB), and j represents a second parameter corresponding to a decimal value other than said consecutive zero bits. The interleaving apparatus and method sequentially stores N input data bits in an interleaver memory with the new interleaver size N′ from an address0to an address N−1. The interleaving apparatus and method then executes a Partial Bit Reversal(PBRO)-interleaving the memory with the new interleaver size N′, and reads data from the memory by deleting addresses corresponding to addresses of N to N′−1 of the memory before interleaving.

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