Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2003-03-05
2004-06-29
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S737000, C257S738000, C257S774000
Reexamination Certificate
active
06756687
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuit packaging, and in particular to flip chip packaging. More specifically, the invention relates to compositions and techniques for strengthening the interfacial bond between a flip chips package substrate and the solder balls used for external electrical connection of the completed flip chip package.
2. Description of Related Art
In integrated circuit packaging, a semiconductor die (also referred to as an integrated circuit (IC) or “chip”) may be bonded directly to a packaging substrate, without the need for a separate leadframe or for separate I/O connectors (e.g., wire or tape). Such chips are formed with ball-shaped beads or bumps of solder affixed to their I/O bonding pads. During packaging, the chip is “flipped” onto its active circuit surface so that the solder bumps form electrical connections directly between the chip and conductive traces on the packaging substrate. Semiconductor chips of this type are commonly called “flip chips.”
Integrated circuits are normally mounted on a printed circuit board (PCB) for use in an electronic device. Electrical connections of a flip chip package are generally made via a solder ball grid array (BGA) formed on the opposite side (referred to herein as the underside) of the packaging substrate from the chip. An unmounted flip chip package with a BGA arranged on its underside is aligned with a PCB and the package and board are then electrically connected in a solder reflow operation in which the solder is heated above its melting temperature and bonds with electrical contacts on the board upon cooling.
As semiconductor technology advances, the gate density of integrated circuits has increased. The substrate of choice for high density flip chip packages is produced by electroless nickel immersion gold (ENIG) technology. ENIG deposition processes provide flat, uniform metal surface finishes with excellent solderability, hardness, wear and corrosion resistance. As a result, ENIG processing has become widespread in BGA component packaging.
Unfortunately, it has been discovered that some solder joints in the BGA become fractured after surface mounting of the BGA package on a PCB where ENIG processing is used (See, for example, Goyal, et al., “Failure Mechanism of Brittle Solder joint Fracture in the Presence of Electroless Nickel Immersion Gold (ENIG) Interface,” Proceedings of the 52
nd
Electronic Component and Technology Conference, 732-739 (May, 2002)). The fracture occurs at the interface of a solder an the ENIG deposited surface. The cause of the fracture and/or susceptibility to fracture has been identified as residual phosphorus from the ENIG process that results in formation of a nickel-phosphorus layer at the nickel solder interface. Such brittle, interfacial solder joint fractures represent a significant reliability issue for high density flip chip package components. Nevertheless, ENIG processed flip chip package substrates have become standard in the industry and thus their continued use would be desirable.
Accordingly, what is needed are compositions and/or methods to reduce the occurrence of brittle, interfacial solder joint fractures at ENIG processed flip chip package substrates and PCBs.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides a flip chip package, apparatus and technique in which a ball grid array composed of a doped eutectic Pb/Sn solder composition is used. The dopant in the Pb/Sn solder forms a compound or complex with the phosphorous residue from the electroless nickel plating process that is mixable with the Pb/Sn solder. The phosphorous containing compound or complex. The phosphorous containing compound or complex prevents degradation of the solder/under bump metallization bond associated with phosphorus residue. The interfacial solder/under bump metallization bond is thereby strengthened. This results in fewer fractured solder bonds and greater package reliability. The amount of the metal dopant is generally greater than 0.2% by weight, for example about 0.2% to 2.5%, or about 2%. Sample dopants include Al, Fe, Ni, Cu, Zn, Mo and In. An electronic device composed of a package in accordance with the invention mounted on a printed circuit board, and a method of making such an electronic device are also provided.
These and other features and advantages of the present invention are described below where reference to the drawings is made.
REFERENCES:
patent: 6288206 (2001-09-01), Stewart et al.
patent: 6307160 (2001-10-01), Mei et al.
patent: 6445069 (2002-09-01), Ling et al.
patent: 2002/0157241 (2002-10-01), Yamamoto
Goyal, et al, “Failure Mechanism of Brittle Solder Joint Fracture in the Presence of Electroless Nickel Immersion Gold (ENIG) Interface”, Proceedings of the 52ndElectronic Component and Technology Conference, 732-739, May 2002.
Binary Alloy Phase Diagrams Binary Alloy Phase Diagrams, 2nded, Dec. 1990, T.B.B. Massalski (Editor), L. Kacprzak (Editor), H. Okamoto (Editor), P.R. Subramanian (Editor), pp. 2269, 2642, 2644, 2294, 2996, 1449, 1451, 1746-1748.
Altera Corporation
Beyer Weaver & Thomas LLP
Greene Pershelle
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