Interface to full and reduce pin JTAG devices

Details Interface to full and reduce pin JTAG devices Interface to full and reduce pin JTAG devices

2007-10-18

2010-10-19

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000, C714S742000

Reexamination Certificate

active

07818641

ABSTRACT:
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

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“Doing more with less—An IEEE 1149.7 embedded tutorial : Standard for reduced-pin and enhanced-functionality test access port and boundary-scan architecture” by Adam Ley This paper appears in: Test Conference, 2009. ITC 2009. International Publication Date: Nov. 1-6, 2009 On pp. 1-10 ISBN: 978-1-4244-4868-5.
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Whetsel, Lee, “A High Speed Reduced Pin Count JTAG Interface,” IEEE p. 10.1, 2006, pp. 1-10.

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