Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1999-12-13
2003-01-14
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
Reexamination Certificate
active
06507899
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an interface for a memory unit in particular to a microprocessor having a memory unit and an interface for coupling the memory unit with the central processing unit. One of the main factors, which determine the speed of a microprocessor, is defined by the interface between the central processing unit and the memory. Therefore, modern microprocessors have a fast cache or static random access memory (SRAM) on-chip to minimize access delays due to external memory access. These cache or SRAM memories have a very low access time and are capable of retrieving or writing data within up to only one processor cycle. If a memory unit, such as a cache memory, is capable of writing and reading data within one single processor cycle, the system would have the fastest possible access to data stored in this memory. Nevertheless, modern microprocessors or microcontrollers have a pipelined structure. In other words, each complete processing of an instruction is split up in several stages, such as fetching an instruction, decoding it, executing it, and writing back the result. These pipeline stages are executed sequentially and usually each pipeline stage is filled with a part of a different instruction. By execution of a plurality of instructions this provides the ability for a microprocessor in average to execute an instruction in one cycle. The more pipeline stages a processor has the more these stages will be diversified.
Due to characteristics of a pipelined microprocessor writing data within one single processor cycle can become impossible because the address and the data are not present at the same time. In such a system, usually the data to be written is available within a delay time (latency) of one cycle after the address is generated because each is generated in a different pipeline stage. As in a reading instruction data will be provided by the memory, only the memory access delay occurs and reading instructions can be executed in one cycle if the memory is fast enough. But, whenever a reading follows a writing the system will be delayed due to the above mentioned latency restrictions.
SUMMARY OF THE INVENTION
It is therefore object of the invention to provide an interface between a memory unit and a data handling unit, such as a central processing unit of a microprocessor or a microcontroller, which allows the fastest access to the memory. For example, a synchronous SRAM demands address and data simultaneously to perform with the highest possible operation speed.
This object is achieved by an interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output. The interface circuit comprises an address buffer having an input and an output, whereby the input receives an address signal from the data handling unit, a first multiplexer which couples the memory unit with either the output of the address buffer or with the address signal, a data buffer having an input and an output, the input receiving a data signal from the data handling unit and the output being coupled with the memory data input, a second multiplexer for selecting either the memory data signal output or the data buffer output, and a comparator for comparing the address signal with the signal from the address buffer output, generating a control signal which controls the second multiplexer.
The interface circuit can be implemented within a microprocessor or within a memory device. Most advantageously it is implemented in a microcontroller having a microprocessor and memory integrated on a single chip.
A further embodiment is an interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output. The interface comprises a first address buffer having an input and an output, whereby the input receives an address signal from the data handling unit. A second address buffer has an input and an output, whereby the input is coupled with the output of the first address buffer. A first multiplexer has inputs and an output and couples either the content of the first or second address buffer to its output. A second multiplexer which couples the memory unit with either the output of the first multiplexer or with the address signal is further provided. A data buffer has an input and an output, whereby the input receives a data signal from the data handling unit and the output is coupled with the memory data input. A third multiplexer for selecting either the memory data signal output or the data buffer output is provided. Furthermore, the interface comprises a comparator for comparing the content of the first and second address buffer, generating a control signal which controls the third multiplexer.
Furthermore, a method of writing data to an integrated memory unit within a microprocessor having a pipeline structure in which a data signal to be written into said memory is delayed with respect to an address signal is disclosed. The method comprises the steps of:
buffering said address signal,
in case of a following write signal, storing said data signal under said buffered address signal, and buffering said following address signal, and
in case of a following read signal, buffering said data signal.
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Baror Gigy
Henftling Manfred
Margalit Niv
Martelloni Yannick
Oberlaender Klaus
Ellis Kevin L.
Fish & Richardson P.C.
Infineon Technologies North American Corp.
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