Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-12-27
2005-12-27
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S062000
Reexamination Certificate
active
06981189
ABSTRACT:
There is disclosed an interface circuit capable of correcting the resistance value of a terminator according to a change in an ambient temperature or the like without causing any distortion in an output waveform during data transmitting, and any reception errors during data receiving. In this case, the interface circuit comprises: a data input/output terminal; a data driver; a data receiver; terminators corrected for resistance values; a detection circuit; and a correction circuit. The detection circuit detects the stoppage of data transmitting/receiving by detecting the predetermined states of potentials respectively of a D+ terminal and a D− terminal. The correction circuit outputs a control signal CTRL to each of the terminators when the result of the detection by the detection circuit shows the stoppage of the data transmitting/receiving. The resistance value of each of the terminators is corrected in response to the control signal CTRL outputted from the correction circuit.
REFERENCES:
patent: 6294932 (2001-09-01), Watarai
patent: 6509755 (2003-01-01), Hernandez-Marti
patent: 2002/0145443 (2002-10-01), Partow et al.
Oki Electric Industry Co. Ltd.
Rabin & Berdo PC
Tu Christine T.
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