Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-16
2002-05-07
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S381000
Reexamination Certificate
active
06383858
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a capacitor for use in an integrated circuit and, more specifically, to a capacitor having interdigitated electrode elements that can be used in an integrated circuit and a method of manufacture therefore.
BACKGROUND OF THE INVENTION
Passive components such as capacitors are extensively used in integrated circuit (IC) design for radio-frequency (RF) and mixed-signal applications, such as bypassing, interstage coupling, and in resonant circuits and filters. Due to the trends toward higher-levels of integration to achieve reduction in cost associated with IC fabrication processes, the integrated IC industry continually strives to economize each step of the IC fabrication process to the greatest extent possible, while maintaining the highest degree of quality and functionality as possible.
One semiconductor device, which has found extensive application in ICs, is the capacitor. The IC industry has devised various types of capacitors for use in both complementary metal oxide semiconductor (CMOS) and Bipolar CMOS devices. Two types of capacitors that the IC industry has developed are metal on metal (MOM) and poly on poly (POP) capacitors. With these devices, the IC industry is able to attain very precise capacitance values in analog circuits. A benefit of MOM and POP capacitors is that they are able to achieve a high capacitance value for a small area. MOM capacitors are commonly formed on a silicon substrate by depositing a first metal layer of titanium (Ti), followed by the deposition of a titanium nitride (TiN) layer, which serves as one of the capacitor's electrodes. A capacitor dielectric material is then deposited over the TiN. Following the deposition of the capacitor dielectric layer, a metal, which serves as the other capacitor's electrode, is deposited over the dielectric layer. The various layer are then patterned and etched to form the desired capacitor structure. Often these MOM and POP capacitors will be formed within an opening in a dielectric material.
POP capacitors are formed in much the same way as the MOM capacitors with the exception that at least one of the electrodes, if not both, comprises polysilicon that is doped to achieve the desired degree of conductance.
A drawback of MOM and POP capacitors is the number of processing steps used to form such capacitors. Both of these structures require additional mask-steps during the IC manufacturing process, which directly translates into added cost. With each processing step, the manufacturing cost of the integrated circuit increases, and due to the competitive market that exists in the IC fabrication industry, any additional cost is highly undesirable. Thus, the IC industry constantly looks for ways to streamline its processes to provide the market with a lower cost, high quality, integrated circuits.
Accordingly, what is needed in the art is a capacitor structure which continues to provide accurate capacitance values and high capacitance values per unit area, but that is capable of being manufactured using the least number of processing steps possible and thereby, saving manufacturing costs.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a capacitor structure comprising an array having two dimensions and having first and second electrode elements alternating in both dimensions of the array. The first electrode elements are interconnected and the second electrode elements are interconnected in such a way to cause the array to function as a capacitor. The capacitor structure further comprises a dielectric material that separates the first and second electrode elements in both of the dimensions. In a preferred embodiment, the dielectric material may be silicon dioxide (SiO
2
). However, other well known semiconductor dielectric materials may be used, such as a tantalum pentoxide or silicon nitride. In one embodiment, the first electrode elements are interconnected by a first interconnect, and the second electrode elements are interconnected by a second interconnect.
Thus, in a broad scope, the present invention provides an interdigitated capacitor structure. The interdigitated capacitor structure allows for increased capacitance values by taking advantage of the high sidewall capacitance that arises from the array of first and second electrode elements in the capacitor structure.
In one aspect of the invention, the capacitor structure has a width of about 50 &mgr;m and has a capacitance value of about 20 fF/&mgr;m. However, one having skill in the art knows the width of the capacitor structure could be greater or less than about 50 &mgr;m, and could have a capacitance value of greater or less than about 20 fF/&mgr;m.
In another embodiment of the invention, the first and second electrode elements comprise copper. However, in a different embodiment the first and second electrode elements may comprise a conductive material selected from the group consisting of doped polysilicon, aluminum or combinations thereof. In the embodiment that uses copper, a barrier layer that is located between the first electrode elements and second electrode elements, and the dielectric materials, may be required. The barrier layer may comprise tantalum nitride (TiN) or any other suitable material known to those who are skilled in the art. The presence of the barrier layer may, of course, depend on the material composition of the electrode element being used. Once the material from which the electrode will be formed is chosen, the appropriate barrier layer material may be selected, if the barrier layer is so required.
Another aspect of the present invention provides a method of fabricating the capacitor structure. In this embodiment, the method includes (1) forming an array having two dimensions and having first and second electrode elements alternating in both dimensions of the array, the first electrode elements interconnected and the second electrode elements interconnected, to cause the array to function as a capacitor; and (2) forming dielectric material between the first and second electrode elements in both of the dimensions.
In yet another aspect, the present invention provides an IC. This particular embodiment includes transistors located on a semiconductor wafer substrate, which may in one embodiment, form a CMOS or a Bipolar device. The IC also includes interconnects located within dielectric layers positioned over the transistors. The interconnects connect the transistors together to form an operative IC. The capacitor structure as just described above is also included in this particular embodiment.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 5208725 (1993-05-01), Akcasu
patent: 5763911 (1998-06-01), Matthews et al.
patent: 5798559 (1998-08-01), Bothra et al.
patent: 5939766 (1999-08-01), Stolmeijer et al.
patent: 6030896 (2000-02-01), Brown
Gupta Rohini
Tauke John D.
Agere Systems Guardian Corp.
Tsai Jey
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