Interconnection structure of integrated circuit chip

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S584000, C257S734000

Reexamination Certificate

active

07732319

ABSTRACT:
An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

REFERENCES:
patent: 6413863 (2002-07-01), Liu et al.
patent: 7005752 (2006-02-01), Bojkov et al.
patent: 2003/0116845 (2003-06-01), Bojkov et al.
patent: 2003/0205628 (2003-11-01), Aizawa et al.
patent: 2004/0067604 (2004-04-01), Ouellet et al.
patent: 2000-208553 (2000-07-01), None
patent: 1999-0055460 (1999-07-01), None
patent: WO 00/72380 (2000-11-01), None
English language abstract of Korean Publication No. 1999-0055460.
English language abstract of Japanese Publication No. 2000-208553.

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