Interconnect testing using non-compatible scan architectures

Details Interconnect testing using non-compatible scan architectures Interconnect testing using non-compatible scan architectures

1994-06-30

2000-02-22

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714733, G01R 3128

Patent

active

060292636

ABSTRACT:
A method is provided that provides a test of an interconnect that communicates information between two digital circuits. One of the digital circuits is constructed to be "scannable" so that it at least includes scannable registers capable of applying signals to, and sampling signals at, the interconnect. The other digital circuit has a different scan architecture such as, for example, that specified by IEEE Standard 1149.1. The method allows the interconnect between the two digital circuits, each having scan architecture that is not compatible with that of the other, to be tested.

REFERENCES:
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patent: 5260950 (1993-11-01), Simpson et al.
patent: 5390191 (1995-02-01), Shiono et al.
patent: 5444715 (1995-08-01), Gruetzner et al.
patent: 5448166 (1995-09-01), Parker et al.

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