Interconnect structure and method for forming the same

Details Interconnect structure and method for forming the same Interconnect structure and method for forming the same

2005-08-31

2010-06-01

Such, Matthew W (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S773000, C257S774000, C257SE23145, C257SE21627, C438S639000, C438S640000, C438S964000

Reexamination Certificate

active

07727888

ABSTRACT:
An interconnect structure and a method for forming the same are described. Specifically, under the present invention, a gouge is created within a via formed in the interconnect structure before any trenches are formed. This prevents the above-mentioned trench damage from occurring. That is, the bottom surface of the trenches will have a roughness of less than approximately 20 nm, and preferably less than approximately 10 nm. In addition to the via, gouge and trench(es), the interconnect structure of the present invention includes at least two levels of metal wiring. Further, in a typical embodiment, the interconnect structure utilizes any dielectrics having a dielectric constant no greater than approximately 5.0.

REFERENCES:
patent: 4184909 (1980-01-01), Chang et al.
patent: 4888087 (1989-12-01), Moslehi et al.
patent: 5427827 (1995-06-01), Shing et al.
patent: 5933753 (1999-08-01), Simon et al.
patent: 5985762 (1999-11-01), Geffken et al.
patent: 6169010 (2001-01-01), Higashi
patent: 6429519 (2002-08-01), Uzoh
patent: 6485618 (2002-11-01), Gopalraja et al.
patent: 6605532 (2003-08-01), Parekh et al.
patent: 6613664 (2003-09-01), Barth et al.
patent: 6616855 (2003-09-01), Chen et al.
patent: 6642146 (2003-11-01), Rozbicki et al.
patent: 6649531 (2003-11-01), Cote et al.
patent: 6784105 (2004-08-01), Yang et al.
patent: 6878615 (2005-04-01), Tsai et al.
patent: 7135402 (2006-11-01), Lin et al.
patent: 7192871 (2007-03-01), Maekawa et al.
patent: 7196002 (2007-03-01), Su et al.
patent: 2003/0011076 (2003-01-01), Seo et al.
patent: 2003/0077897 (2003-04-01), Tsai et al.
patent: 2003/0166345 (2003-09-01), Chang
patent: 2004/0166666 (2004-08-01), Usami
patent: 2005/0106847 (2005-05-01), Hiruta et al.
patent: 2005/0112864 (2005-05-01), Clevenger et al.
patent: 2005/0173799 (2005-08-01), Jou et al.
patent: 2006/0160362 (2006-07-01), Huang et al.
patent: 2006/0172530 (2006-08-01), Cheng et al.
patent: 2007/0202689 (2007-08-01), Choi et al.
Yang, C.C., et al. “Extendability of PVD Barrier/Seed for BEOL Cu Metallization.” Proceedings of the 2005 IEEE International Interconnect Technology Conference (Jun. 6-8, 2005): pp. 135-137.
Liang, Mong-Song, “Challenges in Cu/Low-K Integration,” IEEE Int. Electron Devices Meeting, Jan. 2004, IEEE Publication No. 0-7803-8684-1/04.
Edelstein, D. et al., “Comprehensive Reliability Evaluation of a 90 nm CMOS Technology with Cu/PECVD Low-K BEOL,” IEEE Int. Reliability Physics Symposium 2004.

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