Interconnect methods and apparatus

Details Interconnect methods and apparatus Interconnect methods and apparatus

1996-06-20

1998-11-03

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438618, H01L 21336, H01L 214736

Patent

active

058307974

ABSTRACT:
A damascene method of forming planarized interconnects between conductive material layers in trench-isolated cells in an integrated circuit is disclosed. The method includes depositing and patterning a photoresist layer over a portion of an integrated circuit with isolated devices to expose a portion of an isolation trench separating the conductive layers of isolated devices desired to be interconnected. The method further involves etching a portion of the trench refill material, removing the photoresist layer, and depositing a second conductive layer in the trench to replace the material removed by the etching step. The invention also relates to an interconnected, optionally planarized structure that includes a substrate with an isolation trench defining a first device region and a second device region, a first conductive material in the first and second device regions and adjacent to the trench, a layer of first dielectric material in the trench and adjacent to the first conductive material, and a second conductive material in the trench and overlying the first dielectric material and adjacent to the first conductive material.

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IEDM 95, pp. 907-910, 1995, K.P. Lee, et al., "A Process Technology for 1 GIGA-BIT DRAM".

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