Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-16
2003-01-28
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S629000, C438S649000, C438S672000, C438S651000
Reexamination Certificate
active
06511879
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing such a device, wherein signal lines (e.g., bit lines of a memory device, etc.) may be isolated from adjacent electrical conductors.
2. Discussion of the Related Art
Modern integrated circuit designers confront problems related to the need for increasingly smaller size and higher levels of integration. In the art of integrated circuit fabrication, and particularly when dealing with modern memory circuits, circuit manufacturers must design memory cells that are more densely constructed such that the basic elements making up the cell are closer together. This increasingly close proximity of the discrete electrical features within a memory cell, such as dynamic random access memory (DRAM) cells, becomes problematic in light of the increasing potential for shorting between adjacent electrical conductors. This shorting may cause a memory cell to function improperly or not at all.
An additional concern in the manufacture of integrated circuits is the increasing complexity and cost related to the necessity for diminishing size of the memory devices. The desire to utilize fewer stages of fabrication has led designers of memory cells to strive to simultaneously perform, at a given stage of fabrication, as many necessary steps as possible. An example of this may be seen in the standard technology of fabricating capacitor-over-bit-line (COB) type DRAM cells, which typically employs a process wherein all contacts to the memory cell active area are formed simultaneously. Thus, both bit line and capacitor contacts to the semiconductor substrate are formed using a single layering and etching step (utilizing material such as polysilicon), which creates contact studs over which the additional features of the memory cell are fabricated.
Specifically in a process such as described above, after the contact studs are formed in the memory cell, a dielectric layer is deposited and a bit line contact-hole pattern is lithographically delineated and subsequently etched down to the top of the stud corresponding to the bit line connection to the active area on the substrate below. A plug is next formed within each contact-hole, typically of doped polysilicon, and the conductive layers for the bit lines (typically silicide, polycide, or tungsten-based material) are deposited and subsequently delineated using lithographic-etching techniques. An interlayer dielectric is next deposited around the bit line and a capacitor contact-hole pattern is lithographically delineated and etched down between the formed bit lines to the tops of the studs corresponding to the capacitor bottom electrode connections to the active area on the substrate below. This fabrication step is completed when the capacitor contact-holes are then plugged with doped polysilicon or another conductor. Then the process of cell fabrication continues on to the formation of the capacitor features.
This standard method of fabricating memory cells utilizes the single-step forming of contact studs for both capacitors and bit lines, and the forming of bit line contacts and bit lines. Though this method is useful in reducing the steps required to form contacts to active areas of a substrate, it is desirable that the contacts, and subsequently the fully formed features, be located in a more densely packed array. It is also desirable to have the electrical features and interconnects, exemplified by bit line and capacitor features, arranged in such a more densely packed array without increasing the probability of shorting.
SUMMARY OF THE INVENTION
The present invention relates to integrated circuit fabrication and more particularly to selectively electrically connecting an electrical interconnect line with an associated contact to an active area and electrically isolating the interconnect line from other underlying contacts for other electrical features.
More specifically, in this invention a first interconnect line is formed over two underlying contact holes such that it is electrically connected to a first polysilicon stud but is electrically isolated from a second stud. The line is essentially formed over the first stud and partially over the second stud, and is thereafter electrically isolated from the second studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration.
The present invention also provides a method for efficiently connecting interconnect lines to a plurality of selected contact studs while maintaining electrical isolation from other non-selected plugs.
The above-described and other advantages and features of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.
REFERENCES:
patent: 5155056 (1992-10-01), Jeong-Gyoo
patent: 5422315 (1995-06-01), Kobayashi
patent: 5670404 (1997-09-01), Dai
patent: 5686747 (1997-11-01), Jost et al.
patent: 5801443 (1998-09-01), Ohno
patent: 5847463 (1998-12-01), Trivedi et al.
patent: 5891513 (1999-04-01), Dubin et al.
patent: 5895239 (1999-04-01), Jeng et al.
patent: 5918120 (1999-06-01), Huang
patent: 5935766 (1999-08-01), Cheek et al.
patent: 5968333 (1999-10-01), Nogami et al.
patent: 5981380 (1999-11-01), Trivedi et al.
patent: 6060351 (2000-05-01), Parekh et al.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Tsai Jey
LandOfFree
Interconnect line selectively isolated from an underlying... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interconnect line selectively isolated from an underlying..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnect line selectively isolated from an underlying... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3008054