Interconnect line formed by dual damascene using dielectric...

Details Interconnect line formed by dual damascene using dielectric... Interconnect line formed by dual damascene using dielectric...

2000-09-29

2003-02-04

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S317000, C438S629000, C438S637000, C438S638000, C216S016000

Reexamination Certificate

active

06514671

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the fabrication of semiconductor device interconnect lines and via plugs which are fabricated using dual damascene techniques.
BACKGROUND OF THE INVENTION
A semiconductor device such as an IC (integrated circuit) generally has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Advances in semiconductor materials and processing techniques have resulted in reducing the overall size of the IC circuit elements while increasing their number on a single body. Additional miniaturization is highly desirable for improved IC performance and cost reduction. Interconnects provide the electrical connections between the various electronic elements of an IC and they form the connections between these elements and the device's external contact elements, such as pins, for connecting the IC to other circuits. Typically, interconnect lines form the horizontal connections between the electronic circuit elements while conductive via plugs form the vertical connections between the electronic circuit elements, resulting in layered connections.
A variety of techniques are employed to create interconnect lines and via plugs. One such technique involves a process generally referred to as dual damascene, which includes forming a trench and an underlying via hole. The trench and the via hole are simultaneously filled with a conductor material, for example a metal, thus simultaneously forming an interconnect line and an underlying via plug. Examples of conventional dual damascene fabrication techniques are disclosed in Kaanta et al., “Dual Damascene: A ULSI Wiring Technology”, Jun. 11-12, 1991, VMIC Conference, IEEE, pages 144-152 and in U.S. Pat. No. 5,635,423 to Huang et al., 1997.
An example of a prior art dual damascene technique is illustrated in
FIGS. 1A-1C
, showing various IC structures. As depicted in
FIG. 1A
, a dielectric layer
110
is deposited on a semiconductor substrate
112
. An etch mask
116
, having a via pattern
118
, is positioned on dielectric layer
110
. A timed anisotropic etch is utilized to etch a hole
120
in layer
110
conforming to the via pattern. Mask
116
is subsequently replaced by mask
122
(
FIG. 1B
) having a trench pattern
124
. A timed anisotropic etch is used to form trench
126
and to simultaneously deepen hole
120
to form via hole
128
. This via hole can be etched to expose semiconductor substrate
112
. Alternatively, the via hole can be over-etched partly into the substrate. As illustrated in
FIG. 1C
, the via hole and trench are then filled simultaneously with a suitable metal
130
. Metal
130
thus forms a metallized interconnect line
132
and a via plug
134
which is in contact with semiconductor substrate
112
. Additionally, a liner or barrier layer may be deposited inside the via hole and the trench prior to deposition of the interconnect metal and the via plug. The surface of layer
110
is planarized to remove excess metal
130
and to define interconnect line
132
. Alternately, metal etch-back can be utilized to define the line.
Another example of prior art dual damascene is shown in IC structures illustrated in
FIGS. 2A-2C
. As depicted in
FIG. 2A
, a first dielectric layer
210
is deposited on a semiconductor substrate
212
. An etch stop layer
216
, is deposited on first dielectric layer
210
. A second dielectric layer
218
is deposited on etch stop
216
, and an etch mask
220
is positioned on dielectric layer
218
. Etch mask
220
is patterned (
221
) for etching a via hole. Second dielectric layer
218
is etched using a first anisotropic etch procedure, to form a hole
222
(
FIG. 2A
) conforming to the via pattern. This etching procedure is stopped at etch stop layer
216
. Etch mask
220
is removed and another etch mask
224
(see,
FIG. 2B
) is positioned on second dielectric layer
218
such that it is patterned (
226
) for forming a trench. A second anisotropic etch procedure is used to etch trench
228
in layer
218
. Simultaneously, hole
222
is extended to substrate
212
, by etching through etch stop layer
216
and through first dielectric layer
210
. In this dual damascene technique the first etch procedure has a greater selectivity to etch stop layer
216
than the second etch procedure. As shown in
FIG. 2B
, the second etch procedure results in forming trench
228
and via hole
230
which extends to semiconductor substrate
212
. Mask
224
is removed, after which trench
228
and via hole
230
are simultaneously filled with a suitable conductive metal
232
(see,
FIG. 2C
) forming metallized line
234
and via plug
236
which contacts substrate
212
. Excess metal
232
is removed from the surface of layer
218
to define line
234
.
Conventional dual damascene techniques, such as those exemplified above, have shortcomings for meeting the present and future requirements for reduced design rule and reduced via plug height. For example, the techniques described in connection with
FIGS. 1A-1C
utilize a timed etch. As is well known to those of ordinary skill in the art, it is very difficult to precisely control the etching depth when using a timed etch method. Lack of precise etching control can cause quality problems. The etch stop technique described in connection with
FIGS. 2A-2C
provides more etching control than a timed etch. However, this prior art technique requires the use of an additional layer, i.e. the etch stop layer. Using an additional layer results in a more complex manufacturing process.
Accordingly, a need exists for cost effective, improved methods and materials for dual damascene fabrication, such as eliminating or reducing the number of etch stop layers.
SUMMARY OF THE INVENTION
The present invention provides novel methods and structures for dual damascene containing integrated circuit devices which overcome the prior art problems described above.
In one embodiment of the present invention, a first dielectric layer is deposited on a substrate, such as a semiconductor substrate. This is followed by the deposition of a second dielectric layer on the first dielectric layer. The first and second dielectric layers have dissimilar etching characteristics, i.e. the etching properties of these two layers are such that one of the layers has a higher etch rate compared to the other layer in a specific etch chemistry. A first etch mask patterned for a via hole is provided on the second dielectric layer. The via pattern is then transferred through both dielectric layers by means of anisotropic etching. After removing the first etch mask, a second etch mask is provided on the second dielectric layer, this mask has a trench pattern which is positioned over the underlying via hole. The trench is anisotropically etched through the second dielectric layer using the first dielectric layer as an etch stop. Etch chemistry which is used for etching the trench is such that the second dielectric layer has a higher etch rate compared to the first dielectric layer. These inventive etch procedures result in a trench and an underlying via hole wherein the trench extends through the second dielectric layer while the via hole extends through the first dielectric layer. The second etch mask is removed, the trench and via are then filled simultaneously with a conductive material such as a metal, to form a dual damascene structure. Etch masks used in this embodiment can comprise photoresists, hard masks, or combinations of photoresist and hard masks, depending on the requirements for etching resistance to the etch chemistries which are used to etch the dielectric layers.
In another embodiment of the present invention, a first dielectric layer is deposited on a cap layer which is formed on a semiconductor substrate. A second dielectric layer is deposited on the first dielectric layer, such that the first and se

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