Interactive method for self-adjusted access on embedded DRAM mem

Details Interactive method for self-adjusted access on embedded DRAM mem Interactive method for self-adjusted access on embedded DRAM mem

1998-01-14

2000-03-28

Nelms, David

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

36518901, 365210, G11C 1604, G11C 702

Patent

active

060440244

ABSTRACT:
An embedded memory macro device includes a memory system and a logic circuit constructed on a common semiconductor substrate. The memory system and logic circuit communicate through a handshake procedure via a system data interlock signal. During read cycles the memory system uses the system data interlock signal to tell the logic circuit when data at memory system data outputs is valid. In the preferred embodiment, during write cycles the memory system uses the system data interlock signal to tell the logic circuit when data has been successfully written. The logic circuit needs to wait only until the system data interlock signal permits it to proceed. It then signals the memory system to reset the system data interlock signal and can immediately initiate a new read or write cycle.

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