4. Static information storage and retrieval
  5. Read/write circuit
  6. Including specified plural element logic arrangement

John E. Barth

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High performance gain cell architecture

Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate

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Interactive method for self-adjusted access on embedded DRAM mem

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
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Structures for wafer level test and burn-in

Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate

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Structures for wafer level test and burn-in

Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate

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Profile ID: LFUS-PAI-P-1398481

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