Interactive interface resource allocation in a behavioral...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C718S001000

Reexamination Certificate

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10313775

ABSTRACT:
A behavioral synthesis tool that allows a designer to design an integrated circuit using a generic programming language, such as ANSI C or C++, without the need to include timing information into the source code. In one aspect, the source code is read into the behavioral synthesis tool and the user may dynamically allocate interface resources to the design. In another aspect, the dynamic allocation is accomplished through user input, such as a GUI, a command line, or a file. In another aspect, the behavioral synthesis tool automatically analyzes variables in the source code description and assigns the variables to interface resources. In yet another aspect, the variables and interface resources associated with the variables may be displayed in a hierarchical format in a GUI. In still another aspect, the GUI may allow for expanding and collapsing of different layers in the hierarchy. The GUI may also allow for drag-and-drop operations for modifying the allocation of variables to interface resources.

REFERENCES:
patent: 3624616 (1971-11-01), Patel
patent: 4527249 (1985-07-01), Van Brunt
patent: 5404319 (1995-04-01), Smith et al.
patent: 5428740 (1995-06-01), Wood et al.
patent: 5541850 (1996-07-01), Vander Zanden et al.
patent: 5555201 (1996-09-01), Dangelo et al.
patent: 5623419 (1997-04-01), Kundert
patent: 5625580 (1997-04-01), Read et al.
patent: 5634115 (1997-05-01), Fitzpatrick et al.
patent: 5673198 (1997-09-01), Lawman et al.
patent: 5727187 (1998-03-01), Lemche et al.
patent: 5764951 (1998-06-01), Ly et al.
patent: 5847969 (1998-12-01), Miller et al.
patent: 5870308 (1999-02-01), Dangelo et al.
patent: 5870588 (1999-02-01), Rompaey et al.
patent: 5880971 (1999-03-01), Dangelo et al.
patent: 5912819 (1999-06-01), Kucukcakar et al.
patent: 6044211 (2000-03-01), Jain
patent: 6053948 (2000-04-01), Vaidyanathan et al.
patent: 6145117 (2000-11-01), Eng
patent: 6195786 (2001-02-01), Raghunathan et al.
patent: 6305006 (2001-10-01), Markov
patent: 6314552 (2001-11-01), Markov
patent: 6467075 (2002-10-01), Sato et al.
patent: 6477683 (2002-11-01), Killian et al.
patent: 6477689 (2002-11-01), Mandell et al.
patent: 6480985 (2002-11-01), Reynolds et al.
patent: 6574708 (2003-06-01), Hayter et al.
patent: 6611952 (2003-08-01), Prakash et al.
patent: 6691301 (2004-02-01), Bowen
patent: 6701501 (2004-03-01), Waters et al.
patent: 6704914 (2004-03-01), Nishida et al.
patent: 6708144 (2004-03-01), Merryman et al.
patent: 6760888 (2004-07-01), Killian et al.
patent: 6769081 (2004-07-01), Parulkar
patent: 6917909 (2005-07-01), Markov et al.
patent: 2002/0097269 (2002-07-01), Batcha et al.
patent: 2004/0143801 (2004-07-01), Waters et al.
patent: 2 637 225 (2003-03-01), None
“Techniques for Rapid Implementation of High-Performance FPGAs from Algorithmic C Specifications” by Shiv Prakash, Andrew Guyler, and Simon Waters of Mentor Graphics Corporation.
“Understanding Behavioral Synthess: A Practical Guide to High-Level Design” by John P. Eliott, Ch. 2, pp. 5-23, and Ch. 9, pp. 155-172, Kluwer Academic Publishers, 1999.
Eliott, John P.,Understanding Behavioral Synthess: A Practical Guide to High-Level Design, Ch. 2, pp. 5-23, and Ch. 9, pp. 155-172, Kluwer Academic Publishers, 1999.
Antao et al., “ARCHGEN: Automated Synthesis of Analog Systems,”IEEE Transactions on Very Large Scale Integration(VLSI)Systems, pp. 231-244 (Jun. 1995).
Antao, “Architectural Exploration for Analog System Synthesis,”Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 529-532 (May 1995).
Antoniazzi et al., “A Methodology for Control-Dominated Systems CoDesign,”Third International Workshop on Hardware/Software Codesign, pp. 2-9 (Sep. 1994).
Arnout, “SystemC Standard,”IEEE, pp. 573-577 (2000).
Buonanno et al., “Application of a Testing Framework on VHDL Descriptions at Different Abstraction Levels,”IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 654-659 (Oct. 1997).
Camposano, “From Behavior to Structure: High Level Synthesis,”IEEE Design&Test of Computers, pp. 8-19 (Oct. 1990).
Camposano et al., “Synthesizing Circuits From Behavioral Descriptions,”IEEE Transactions on Computer-Aided Design, vol. 8, No. 2, pp. 171-180 (Feb. 1989).
Cong et al., “Combinatorial Logic Synthesis for LUT Based Field Programmable Gate Arrays,”ACM Transactions on Design Automation of Electronic Systems, vol. 1, No. 2, pp. 145-204 (Apr. 1996).
Cong et al., “FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 1, pp. 1-12 (Jan. 1994).
De Micheli et al., “The Olympus Synthesis System,”IEEE Design&Test of Computers, pp. 37-53 (Oct. 1990).
Francis et al., “Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs,”Proceedings of the 28th Conference on ACM/IEEE Design Automation Conference, pp. 227-233 (1991).
Fuhrman, “Industrial Extensions to University High Level Synthesis Tools: Making it Work in the Real World,”Proceedings of the 28th Conference on ACM/IEEE Design Automation Conference, pp. 520-525 (Jun. 1991).
Goering, “Cadence Mounts Synthesis Threat,”Electronic Engineering Times, 3 pp., downloaded from http://eetimes.com
ews/97/939news/threat.html (document published in 1997).
Goldberg, “Visual Architect Bridges The Gap Between Systems and ASIC Designers,” 4 pp. downloaded from http:www.edacafe.com/technical/papers/Cadence/archive/vol2No2/visualArc.php.
Hsu et al., “Digital Design From Concept to Prototype in Hours,”IEEE Asia-Pacific Conference on Circuits and Systems, pp. 175-181 (Dec. 1994).
Jemai et al., “Architectural Simulation in the Context of Behavioral Synthesis,”Proceedings of the Design Automation and Test in Europe, pp. 590-595 (Feb. 1998).
Kim et al., “Utilization of Multiport Memories in Data Path Synthesis,”Proceedings of the 30th ACM/IEEE Design Automation Conference, pp. 298-302 (1993).
Kucukcakar et al., “Matisse: An Architectural Design Tool For Commodity ICs,”IEEE Design&Test of Computers, vol. 15, Issue 2, pp. 22-23 (Apr.-Jun. 1998).
Liao et al., “An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment,”Proceedings of the 34th ACM/IEEE Design Automation Conference, pp. 70-75 (1997).
Lipton et al., “PDL++: An Optimizing Generator Language for Register Transfer Design,”ISCAS-90, pp. 1135-1138 (1990).
Ly et al., “Applying Simulated Evolution to High Level Synthesis,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 389-409 (Mar. 1993).
Ly et al., “Scheduling using Behavioral Templates,”Proceedings of the 32nd ACM/IEEE Design Automation Conference, pp. 101-106 (Jun. 1995).
Marwedel et al., “RAM-Based Architectural Synthesis,” inNovel Approaches in Logic and Architecture Synthesis, pp. 233-244, G. Saucier, Ed. (1995).
McFarland et al., “The High-Level Synthesis of Digital Systems,”Proceedings of the IEEE, vol. 78, No. 2, pp. 301-318 (Feb. 1990).
Middelhoek et al, “From VHDL to Efficient and First-Time-Right Designs: A Formal Approach,”ACM Transactions on Design Automation of Electronic Systems, vol. 1, No. 2, pp. 205-250 (Apr. 1996).
Park et al., “Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 356-370 (Mar. 1988).
Patel, “A Design Representation for High Level Synthesis,”Proceedings of the European Design Automation Conference, pp. 374-379 (Mar. 1990).
Perkowski et al., “Diades, A High Level Synthesis System,”IEEE International Symposium on Circuits and Systems, pp. 1895-1898 (May 1989).
Prakash et a

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