Inter-queue ordering mechanism

Details Inter-queue ordering mechanism Inter-queue ordering mechanism

2006-11-21

2006-11-21

Vo, Tim (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S311000, C710S315000

Reexamination Certificate

active

07139859

ABSTRACT:
A device for implementing transaction ordering enforcement between different queues of a computer system interconnect using an inter-queue ordering mechanism. The device includes first and second circular queues and input and output counters. The queues have an ordering dependency requirement between them such that entries in the second queue are not allowed to pass entries in the first queue. One requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued. Another requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued and then acknowledged as completed. The input and the output counters increment whenever an entry is enqueued to or dequeued from the first queue, respectively. The device may be implemented PCI and PCI-X systems or other interconnect systems.

REFERENCES:
patent: 5881254 (1999-03-01), Corrigan et al.
patent: 6502157 (2002-12-01), Batchelor et al.
patent: 6629179 (2003-09-01), Bashford
patent: 6763402 (2004-07-01), Talati

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