Inter-functional-block restriction high-speed extraction...

Details Inter-functional-block restriction high-speed extraction... Inter-functional-block restriction high-speed extraction...

2000-11-13

2003-04-22

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06553557

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an inter-functional-block restriction high-speed extraction method and a recording medium having stored thereon an inter-functional-block restriction high-speed extraction program to obtain, in a logic synthesis procedure in which the gate conversion and optimization are conducted according to boundary conditions and optimizing conditions of input/output interfaces set for each unit under top-level restriction, timing restriction of boundary sections in a short period of time.
DESCRIPTION OF THE PRIOR ART
In the designing of semiconductor integrated circuits whose size has been increasing these days, a bottom-up procedure or a bottom-up compilation has been generally used in which functions are described and are compiled for each lower-level unit and then the functions resultant from the compilation are combined with each other for one chip.
In the bottom-up compilation, a large-sized semiconductor integrated circuit (design) is first subdivided into units such as functional blocks. For each lower unit, the compilation is conducted using top restriction describing boundary conditions of each input/output interface, optimizing conditions, and the like at a top level. In the compilation, the restriction at the top level as well as restriction for each lower-level unit are required.
When restrictions other than the top-level restriction are to be manually generated, there arise problems in the generation of restrictions. For example, restrictions cannot be easily predicted, creation of scripts takes a long period of time, and errors occurs easily. To solve these problems, there is required a function (to be referred to as “design budget” herebelow) to automatically generate restrictions for all levels from an upper-most level to a lower-most level or a unit level.
FIG. 3
shows, in a flowchart, logic synthesis of the prior art in which a design budget is conducted at a gate level after logic synthesis. Namely, restrictions are generated for lower-level units according to top restriction A
7
and timing is allocated to each unit also according to the top restriction A
7
.
FIG. 2
schematically shows an example of a design
101
including units A
201
, B
301
and C
401
. Each unit A
201
to C
401
includes a boundary section and an another section (an exception of the boundary section or no boundary section). The boundary section controls interfaces for external terminals in design or external input/output buffers and interfaces between units. The boundary section primarily has a function switching (or retiming) at particular clock timing, a signal inputted from a unit or a signal outputted to an external device. Details of the boundary section will be described later. The exception of the boundary section actually implements a primary function of the unit.
In the design
101
, the unit A
201
includes boundary sections
202
,
204
, and
205
and no boundary section
203
. The unit B
301
includes boundary sections
302
,
304
, and
305
and no boundary section
303
. The unit C
401
includes boundary sections
402
,
403
,
405
,
406
, and
407
and no boundary section
404
.
Since the timing restriction of each unit is related only to the interfaces between the units, the unit-level restriction is required for the boundaries of input/output interfaces
202
,
204
,
205
,
302
,
304
,
305
,
402
,
403
,
405
,
406
, and
407
. The compilation is carried out for the overall design
101
.
Referring to
FIGS. 2 and 3
, a logic synthesis procedure of the prior art will be described. The procedure generally includes a first procedure A
1
, a second procedure A
9
, and a third procedure A
11
. In the first procedure A
1
, register-transfer-level (RTL) description A
2
and unit initial restriction A
4
including simple restriction for synthesis of units A
201
, B
301
, and C
401
are inputted to execute a logic synthesis step A
3
.
To achieve a design budget step A
6
for a design resultant from the logic synthesis step A
3
, a boundary extraction step A
5
is conducted to extract the boundary sections
202
,
204
,
205
,
302
,
304
,
305
,
402
,
403
,
405
,
406
, and
407
of the respective units. Using the top restriction A
7
as an input, the design budget step A
6
is executed to resultantly produce timing restriction A
8
.
In the second procedure A
9
, the timing restriction A
8
obtained by the first procedure A
1
and the initial RTL description A
2
are inputted to execute a logical synthesis step A
3
′ for the units A
201
, B
301
, and C
401
. For each design obtained by the step A
3
′, the design budget step A
6
is carried out using the TOP restriction A
7
to generate timing restriction A
8
.
For the timing restriction A
8
, a timing analysis step A
10
is executed to detect timing violation. If a timing violation is detected, control returns to the logical synthesis step A
3
′. When the number of execution of the second procedure A
9
is increased, precision of the processing becomes higher.
In the third procedure A
11
, when a timing violation is not detected as a result of the timing analysis step A
10
of the second procedure A
9
, timing restriction A
8
resultant from the procedure A
9
is inputted to execute a logical analysis step A
12
for each unit. Using a design obtained by the step A
12
and the top restriction A
7
, a logical analysis step A
3
is executed for the top section and then a timing analysis step A
14
is conducted.
Referring to
FIGS. 2 and 4
, description will be given of an example of allocation of timing to each unit according to the top restriction A
7
.
FIG. 4
partly shows a structural example of the boundary sections
204
and
302
respectively of the units A
201
and B
301
shown in
FIG. 2. A
synthesis step is first executed for each unit according to the unit initial restriction A
4
to resultantly obtain delay information of the boundary sections
204
and
302
. The values of delay are respectively 7 nanoseconds (ns) and 5 ns in this case.
Assume that the top restriction A
7
indicates timing information of 10 ns between the units A
201
and B
301
. In this situation, the delay is 12 ns for the restriction of 10 ns and hence a violation of 2 ns results. The top restriction is stipulated by the specifications and hence must be strictly observed.
When the violation of 2 ns is proportionally distributed to the units A
201
and B
301
, 10×{7/(5+7)} and 10×{5/(5+7)} are allocated to the units A
201
and B
301
, respectively. The sum of these values is 10 ns and hence the timing violation is avoided.
By executing the design budget A
6
, the boundary sections
202
,
204
,
205
,
302
,
304
,
305
,
402
,
403
,
405
,
406
, and
407
of the respective units are separated to optimize timing information for each unit. The logic synthesis procedure can also be applied to a large-sized design and minimizes the time required for manual operation in the synthesis.
However, the prior art is attended with the problem as follows. While the design of the logic circuit is increasing in size, it is required for the designer to minimize the time to complete the operation. In this situation, the machine to execute the logic synthesis and the like has not sufficient processing performance. Under the conditions in which time, disk capacity, and machine power are limited, a logic synthesis method has been desired to produce a result of synthesis at a high speed and with high precision while saving human power.
In the logic synthesis method of the prior art, the logic synthesis must be repeatedly carried out to generate restrictions for the lower units according to the TOP restriction A
7
. For each logic synthesis, the compilation must be conducted for all units of FIG.
2
. However, the design budget to generate the restriction for a unit only requires information of the boundary section of the unit, and information regarding most part of the design synthesized is not used. Namely, to repetitiously compi

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