Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1982-05-20
1984-07-17
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365104, 365218, 371 21, G11C 1140
Patent
active
044609825
ABSTRACT:
An E.sup.2 PROM is disclosed which provides automatic programming verification. Before data is written into the cells, the cells are automatically erased. The contents of the cells are checked to verify that erasing has been completed. If it has not, erasing is continued until the cells are erased. When data is written into the cells, the writing of the data into the cells continues until programming is verified. The verification is conducted at potentials other than the normal reference potential to assure that the cells are well programmed with either binary zeroes or binary ones.
REFERENCES:
patent: 4203158 (1980-05-01), Frohmann-Beutchkowsky
patent: 4266283 (1981-05-01), Pergelos
patent: 4363109 (1982-12-01), Gardner
Bobra Yogendra
Cheng Pearl
Gee Lubin
Mehta Rustam
Fears Terrell W.
Intel Corporation
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