Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-17
2007-07-17
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C327S336000
Reexamination Certificate
active
10928179
ABSTRACT:
An input interface circuit is provided which includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.
REFERENCES:
patent: 6470466 (2002-10-01), Takahashi
Connolly Bove & Lodge & Hutz LLP
Lamarre Guy J.
United Microelectronics Corporation
LandOfFree
Integration type input circuit and method of testing it does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integration type input circuit and method of testing it, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integration type input circuit and method of testing it will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3788007