Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-10-31
2006-10-31
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S595000, C257SE21640
Reexamination Certificate
active
07129127
ABSTRACT:
A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown poly oxide layer (212). Offset spacers are formed adjacent to sidewalls of the gate electrodes (216). Extension regions are then formed (214) within the PMOS region and the NMOS region. Sidewall spacers are formed (218) adjacent to the sidewalls of the gate. electrodes. An n-type dopant is implanted into the NMOS region to form source/drain regions and a p-type dopant is implanted with an overdose amount into the PMOS region to form the source/drain regions within the PMOS region (220). A poly cap layer is formed over the device (222) and an anneal or other thermal process is performed (224) that causes the p-type dopant to diffuse into the nitride containing cap oxide layer and obtain a selected dopant profile having sufficient lateral abruptness.
REFERENCES:
patent: 5019882 (1991-05-01), Solomon et al.
patent: 5241197 (1993-08-01), Murakami et al.
patent: 5683934 (1997-11-01), Candelaria
patent: 5849615 (1998-12-01), Ahmad et al.
patent: 5863827 (1999-01-01), Joyner
patent: 5882981 (1999-03-01), Rajgopal et al.
patent: 6004871 (1999-12-01), Kittl et al.
patent: 6087241 (2000-07-01), St. Amand et al.
patent: 6180454 (2001-01-01), Chang et al.
patent: 6211064 (2001-04-01), Lee
patent: 6214699 (2001-04-01), Joyner
patent: 6261964 (2001-07-01), Wu et al.
patent: 6284233 (2001-09-01), Simon et al.
patent: 6284626 (2001-09-01), Kim
patent: 6284633 (2001-09-01), Nagabushnam et al.
patent: 6303486 (2001-10-01), Park
patent: 6368967 (2002-04-01), Besser
patent: 6380029 (2002-04-01), Chang et al.
patent: 6406973 (2002-06-01), Lee
patent: 6495853 (2002-12-01), Holbrook et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6767778 (2004-07-01), Wang et al.
patent: 2003/0111699 (2003-06-01), Wasshuber et al.
U.S. Appl. No. 10/877,154, filed Jun. 25, 2004, Chidambaram.
U.S. Appl. No. 10/901,568, filed Jul. 29, 2004, Chidambaram et al.
Bu Haowen
Chakravarthi Srinivasan
Chidambaram Periannan
Khamankar Rajesh
Brady III W. James
Chaudhari Chandra
Keagy Rose Alyssa
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Integration scheme to improve NMOS with poly cap while... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integration scheme to improve NMOS with poly cap while..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integration scheme to improve NMOS with poly cap while... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3706133