Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-04-22
2003-02-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S631000, C438S633000, C438S642000, C438S652000, C438S658000, C438S659000, C438S672000
Reexamination Certificate
active
06518185
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to a method of forming copper interconnects having high electromigration resistance.
2. Background Art
Recently, copper has received considerable attention as a candidate for replacing aluminum and/or tungsten in wiring and interconnection technology for very large-scale integration (VLSI) and ultra-large-scale integration (ULSI) applications. In particular, copper has a lower resistivity than aluminum or tungsten, and in addition has high conformality and filling capability for deposition in via holes and trenches, along with low deposition temperature.
However, a disadvantage of copper is that it exhibits poor electromigration resistance. That is, with current flow through a copper conductor, copper atoms may migrate to cause a break in the metal.
U.S. Pat. No. 6,022,808 to Nogami et al., issued Feb. 8, 2000, and assigned to the Assignee of this invention (herein incorporated by reference), discloses a method for improving the electromigration resistance of copper in this environment. In furtherance thereof, interconnects are formed in vias and/or trenches in a dielectric by depositing undoped copper, and then a copper layer containing a depant element is deposited on the undoped copper. An annealing step is undertaken to diffuse dopant into the previously undoped copper, thereby improving the electromigration resistance of the copper. Also of general interest is U.S. Pat. No. 6,346,479 to Woo et al., issued on Feb. 12, 2002 and assigned to the Assignee of this invention (herein incorporated by reference).
While this method is significantly advantageous, a device environment with varying feature sizes presents special problems, as will now be described with reference to
FIGS. 1-6
.
FIG. 1
is a cross-section of a semiconductor device
20
illustrating a step in a prior process. As shown therein, a dielectric layer
22
, such as silicon dioxide or other material having a low dielectric constant, is formed above a semiconductor substrate
24
, typically comprising monocrystalline silicon. It should be understood, however, that dielectric layer
22
may be an interlayer dielectric a number of layers above the surface of the semiconductor substrate
24
.
Openings
26
,
28
,
30
,
32
are formed in the dielectric layer
22
using conventional photolithographic and etching techniques. These openings
26
-
32
represent holes for forming contacts or vias or trenches for forming interconnect lines. As shown in
FIG. 1
, openings
26
-
32
each have the same depth, and the widths of the openings
26
,
28
,
30
are substantially the same, while the width of the opening
32
is substantially greater than the widths of the openings
26
,
28
,
30
. Thus, openings
26
,
28
,
30
have high aspect ratios, and opening
32
has a lower aspect ratio. With reference to
FIG. 2
, if chosen, a layer
34
may be included, made up of a diffusion barrier layer deposited over the structure, and a copper seed layer deposited over the diffusion barrier layer, as is well-known and described in the above cited patents.
FIG. 3
illustrates the step of depositing an undoped copper layer
36
over the resulting structure by, for example, electroplating. The undoped copper
36
fills the openings
26
,
28
,
30
,
32
and is deposited to define an upper surface
38
which extends above the dielectric layer
22
. As will be seen in
FIG. 3
, because of the small features defined by the openings
26
,
28
,
30
, and their close proximity, the surface portion
38
A over those openings
26
,
28
,
30
is generally planar in configuration. However, because of the substantially greater width of the opening
32
, the surface portion
38
B over the opening
32
is recessed relative to the surface portion
38
A over the openings
26
,
28
,
30
, causing the overall upper surface
38
of the copper
36
to be substantially non-planar.
Next, as illustrated in
FIG. 4
, a layer of doped copper
40
is sputter deposited on the undoped copper layer
36
. Annealing is then undertaking to difffuse dopant element atoms
42
from doped copper layer
40
into undoped copper layer
36
(FIG.
5
).
During this step, because of the substantial planarity of the surface portion
38
A over the openings
26
,
28
,
30
, the copper
36
in each opening
26
,
28
,
30
will be doped generally to the same concentration. However, because the surface portion
38
B of the copper layer
36
is recessed over the opening (causing reduced volume of copper under the layer
40
adjacent the opening
32
), the concentration of dopant
42
in the copper
36
in opening
32
will be substantially higher. After chemical mechanical polishing (CMP) to provide that the surface of the copper
36
in each opening
26
,
28
,
30
,
32
is coplanar with the upper surface of the dielectric layer
22
, it will be seen that features
36
A,
36
B,
36
C,
36
D are formed, with feature
36
D being of a configuration different from features
36
A,
36
B,
36
C. In accordance with the analysis above, concentration of dopant
42
in the feature
36
D is higher than in any of the features
36
A,
36
B,
36
C, i.e., concentration of dopant
42
is dependent on feature size. Thus, uniformity in electromigration resistance from feature to feature is not achieved.
Therefore, what is needed is a method for providing substantially uniform concentration of dopant material in copper interconnects of the varying features size.
DISCLOSURE OF THE INVENTION
In the present method of fabricating a semiconductor device, openings of different configurations, for example, different aspect ratios are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to increase the planarity of the upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to diffuse the doping element into the copper in the openings.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 6022808 (2000-02-01), Nogami et al.
patent: 6037257 (2000-03-01), Chiang et al.
patent: 6110817 (2000-08-01), Tsai et al.
patent: 6124205 (2000-09-01), Doan
patent: 6207222 (2001-03-01), Chen et al.
patent: 6268291 (2001-07-01), Andricacos et al.
patent: 6346479 (2002-02-01), Woo et al.
patent: 6395628 (2002-05-01), Doan
Adem Ercan
Avanzino Steven
Buynoski Matthew
Marathe Amit
Sahota Kashmir
Advanced Micro Devices , Inc.
Gurley Lynne A.
Niebling John F.
LandOfFree
Integration scheme for non-feature-size dependent cu-alloy... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integration scheme for non-feature-size dependent cu-alloy..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integration scheme for non-feature-size dependent cu-alloy... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3181059