Integration scheme for metal gap fill, with fixed abrasive CMP

Details Integration scheme for metal gap fill, with fixed abrasive CMP Integration scheme for metal gap fill, with fixed abrasive CMP

2005-09-13

2005-09-13

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S693000, C438S959000

Reexamination Certificate

active

06943114

ABSTRACT:
In a method of planarizing a semiconductor wafer, the improvement comprising polishing above metal interconnect lines to uniformly polish the topography of the wafer to a predetermined endpoint on the wafer sufficiently close above the metal interconnect lines, yet far enough away from the lines to prevent damage to the lines, comprising:a) filling gaps between metal interconnect lines of an inter metal dielectric in a wafer being formed, by depositing HDP fill on top of the metal interconnects, between the metal interconnects, and on the surface of a dielectric layer between the metal interconnects to create an HDP overfill;b) contacting the surface of HDP overfill of the processed semiconductor wafer from step a) with a fixed abrasive polishing pad; andc) relatively moving the wafer and the fixed abrasive polishing pad to affect a polishing rate sufficient to reach a predetermined endpoint and uniformly planar surface on the wafer sufficiently close above the metal interconnect lines and yet far enough away from the lines to prevent damage to the lines.

REFERENCES:
patent: 5692950 (1997-12-01), Rutherford et al.
patent: 5795495 (1998-08-01), Meikle
patent: 5850105 (1998-12-01), Dawson et al.
patent: 5897426 (1999-04-01), Somekh
patent: 5958794 (1999-09-01), Bruxvoort et al.
patent: 6007407 (1999-12-01), Rutherford et al.
patent: 6034418 (2000-03-01), Matsuura
patent: 6037278 (2000-03-01), Koyanagi et al.
patent: 6232171 (2001-05-01), Mei
patent: 6232231 (2001-05-01), Sethuraman et al.
patent: 6234875 (2001-05-01), Pendergrass, Jr.
patent: 6310375 (2001-10-01), Schrems
patent: 6325702 (2001-12-01), Robinson
patent: 6350692 (2002-02-01), Economikos et al.
patent: 6435942 (2002-08-01), Jin et al.
patent: 6653242 (2003-11-01), Sun et al.
patent: 6656842 (2003-12-01), Li et al.
patent: 2002/0074311 (2002-06-01), Funkenbusch
patent: 2003/0029212 (2003-02-01), Im
patent: 2003/0176151 (2003-09-01), Tam et al.
patent: 1 068 928 (2001-01-01), None
Wolf, S.,Silicon Processing for the VLSI Era,vol. 2, Lattice Press, Sunset Beach, California (1990) pp. 189-193.
Penka, S., et al., “Integration Aspects of Flowfill and Spin-on-Glass Process for Sub-0.35μm Interconnects,” Interconnect Technology Conference, Proceedings of the IEEE 1998 International (Jun. 1-3, 1998) pp. 271-273.
Mendonca, J., et al., “Interconnect Material and CMP Process Change Effects on Local Interconnect Planarity,” Interconnect Technology Conference, Proceedings of the IEEE 1998 International (1998) pp. 196-198.

Affiliated with

Also associated with

Rating

Integration scheme for metal gap fill, with fixed abrasive CMP does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integration scheme for metal gap fill, with fixed abrasive CMP, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integration scheme for metal gap fill, with fixed abrasive CMP will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3445543