Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2004-01-21
2004-10-19
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000, C438S244000, C438S386000, C438S249000
Reexamination Certificate
active
06806138
ABSTRACT:
BACKGROUND OF INVENTION
The present invention relates generally to semiconductor integrated circuits (ICs), and more particularly to deep trench (DT) capacitors formed within such ICs. This invention also relates to a method for producing such DT capacitors within semiconductor ICs. Such ICs include, for example, memory ICs such as random access memories (RAMs), dynamic RAMs (DRAMs), synchronous DRAMs (SDRAMs), static RAMS (SRAMs), and read only memories (ROMs) or other memory ICs. Other ICs include devices such as programmable logic arrays (PLAs), application-specific ICs (ASICs), merged logic/memory ICs (embedded DRAMs), system-on-chip,(SoC), or any circuit devices utilizing trench capacitors.
A memory cell in an IC typically comprises a transistor and an associated capacitor. The capacitor, which is typically formed in a portion of a trench, consists of a pair of conductive plates, i.e., electrodes, which are separated from each other by a node dielectric material. Information or data is stored in the memory cell in the form of charge accumulated on the capacitor. As the density of ICs with memory cells is increased, the area for the capacitor is decreased and the amount of charge that the capacitor is able to accumulate is reduced. Thus, with less charge to detect, reading the information or data from the memory cell becomes much more difficult.
There are three known techniques for increasing the amount of charge within a limited fixed space or volume for the capacitor of a memory cell in a highly integrated circuit. These three known techniques include: (1) decreasing the thickness of the dielectric material, i.e., node dielectric, that is located between the capacitor plates; (2) changing the dielectric material to one with a dielectric constant higher than silicon oxide or silicon nitride; or (3) increasing the surface area of the space to be used for the capacitor.
The first two solutions have drawbacks associated there-with. For example, solution (1), which thins the capacitor dielectric, also increases leakage currents that may affect the memory retention performance of the capacitor and the reliability of the memory cell. Solution (2), which purports to change the dielectric material to a higher-dielectric material, will cause only a slight improvement in charge storage because the dielectric constant of suitable alternative dielectrics is only slightly higher than the dielectric material currently being used. Moreover, the substitution of alternative dielectrics may be more complicated, more expensive and provide fabrication problems that are heretofore unknown. Accordingly, solution (3), i.e., increasing the surface area of the space to be used for the capacitor, provides the most promise for substantially improving the amount of charge stored without causing any of the problems mentioned for solutions (1) and (2) above.
One previous solution to increase the surface area of the capacitor is to replace common stack capacitor technology with trench capacitors. In common stack capacitor technology, the capacitor is built on a surface created on a semiconductor substrate, whereas in trench capacitor technology, the capacitor is formed within a trench that is formed in a semiconductor substrate itself. As depth of the trench increase, the surface area of the capacitor also increases. However, the depth of the trench is limited by present fabrication methods and tools. This problem is further compounded by the forever increasing density of ICs achieved by dimensional shrinkage. To offset the loss of surface area due to a reduction in width, the depth of the trench must be further increased to the point where the necessary depth is not achievable or becomes prohibitively expensive.
Another method of increasing the surface area of the capacitor is to provide capacitor plates that contain textured or roughened surfaces in-the deep trench adjacent to the dielectric material. A capacitor plate having roughened surface area increases the amount of surface area of the capacitor due to the peaks and valleys of the roughened surface. The depth of the trench is maximized and the rough surface of the plates is designed to give maximum surface area based on a cross-section of the roughened surface so that the surface area is three-dimensional at the interface of the plates and the dielectric material.
For example, U.S. Pat. No. 6,177,696 discloses a trench capacitor in which capacitance is increased by using hemispherical grained silicon (HSG). An amorphous silicon film is deposited on sidewalls of the deep trench, and then converted into a HSG film. The HSG film may be formed either before or after formation of the buried plate for the lower electrode of the deep trench capacitor. The HSG film must be doped with the same dopant as used for the buried plate. Doping of the HSG film may occur either during or after formation of the HSG film. The presence of the doped HSG film on sidewalls of the deep trench increases the surface area of the lower electrode in the deep trench. The remainder of the deep trench capacitor may be formed by depositing node silicon nitride film within the deep trench, and then filling the trench with doped polysilicon film to form the upper electrode. The method of this patent produces a deep trench capacitor having increased surface area on the lower electrode, but subsequent high temperature processing often causes smearing of the amorphous HSG film, such that the HSG film hardly survives in the final product. In addition, increased node leakage current and degraded reliability may be experienced as a result of the HSG film.
In U.S. Pat. No. 6,555,430, another method for increasing the surface area of the lower electrode is disclosed. In this method, an HSG film is formed on lower sidewalls of the deep trench, conventionally using a collar structure to mask upper sidewalls. An oxidation process is then performed so as to oxidize the HSG film as well as exposed portions of the substrate sidewall. The oxidized HSG film and the oxidized portion of the substrate are then removed, leaving a roughened surface on the deep trench sidewall. The buried plate may be formed either before or after the HSG surface enhancement. Performing the HSG oxidation after the buried plate is formed may result in undesired dopant loss in the buried plate. On the other hand, if the HSG oxidation and removal is performed before the buried plate is formed, undesired doping in the upper trench may occur due to collar damage during HSG oxidation and stripping.
Therefore, there remains a need in the art for a method of enhancing the capacitance of trench capacitors. Specifically, there is a need in the art for a simpler and more robust integration scheme to enhance the capacitance of trench capacitors.
SUMMARY OF INVENTION
These and other deficiencies in the prior art are overcome through the method of this invention for enhancing the capacitance of trench capacitors. The invention is directed to a method for forming a deep trench capacitor structure. The method comprises the steps of: (a) forming a deep trench in a semiconductor substrate, the deep trench having an upper region and a lower region; (b) forming a collar on interior walls of the upper region of the deep trench; (c) forming a layer of hemispherical silicon grain on exposed interior walls of the lower region of the deep trench; (d) annealing the substrate in an environment comprising oxygen while simultaneously forming a doped region in the substrate, thereby oxidizing the layer of hemispherical silicon grain and oxidizing a portion of the substrate to form a roughened surface on interior walls of the lower region of the deep trench; and (e) removing the oxidized layer of hemispherical silicon grain and the oxidized portion of the substrate.
In accordance with one aspect of the invention, formation of the doped region in the substrate comprises the steps of: forming a layer of doped material such as arsenic-doped silicate glass (ASG) on the layer of hemispherical silicon grain and on exposed interior walls of the lower reg
Akatsu Hiroyuki
Cheng Kangguo
Divakaruni Rama
International Business Machines - Corporation
Pepper Margaret A.
Rocchegiani Renzo N.
Smith Matthew
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