Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-09
2002-02-19
Neibling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000
Reexamination Certificate
active
06348382
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of performing Lightly Doped Drain (LDD) implants for High Voltage (HV) and for Low Voltage (LV) polysilicon gate electrodes using one processing sequence thereby enabling the creation of devices that contain both HV and LV polysilicon gate electrodes.
(2) Description of the Prior Art
The continuing striving of the semiconductor industry to reduce device manufacturing costs has been accompanied by a simultaneous emphasis on improving device performance. These objectives have been met in the industry by the continued improvements of a number of interrelated technical disciplines. Key among these disciplines are photolithography and the innovative application of materials combined with new methods of applying processing parameters and processing sequences that are used to create the device features and semiconductor devices. Critical to device performance improvements is the reduction of device dimensions. As an example, the performance of typical Metal Oxide Field Effect Transistors (MOSFET) is critically dependent on the dimensions of the gate electrode that is used in the creation of MOSFET devices. This requirement of creating narrow gate features is closely coupled with the process of photolithography that is used in the creation of the gate electrode. The reduction of gate electrode gate size has been made possible by a confluence of improvements in photolithography (allowing for greater image resolution), in improved photoresist material and in the development of high contrast photoresist material.
Improved etching techniques such as Reactive Ion Etching (RIE) have also contributed to the creation of deep sub-micron device features. With improvements in photo-imaging techniques and advancements in exposure methods, the wavelengths of the exposure sources now reach into the Deep Ultra Violet range. Special techniques such as the application of special layers of material further improve focusing depth and sharpness of focus in creating images in for instance layers of photoresist that are applied to create interconnect lines, vias, contact openings and the like. These techniques are equally applied in the formation of for instance Complementary Metal Oxide Semiconductor (CMOS) devices.
The technique of creating complementary n-channel and p-channel devices has long been known and applied in the semiconductor industry. The salient advantage of these devices is their low power usage due to the fact that two transistors are paired as complementary n-channel and p-channel transistors whereby in either logic state (on/off) of the device, one of the two transistors is off and negligible current is carried through this transistor. The logic elements of Complementary Metal Oxide devices drain significant amounts of current only at the time that these devices switch from one state to another state. Between these transitions the devices draw very little current resulting in low power dissipation for the CMOS device.
The invention addresses an improved method of concurrently creating Lightly Doped Drain (LDD) regions in both high voltage and low voltage CMOS devices, following will therefore be a brief overview of present methods of forming these devices.
A typical n-channel transistor for a CMOS inverter is formed by first forming a p-region (also called tub or well) in the surface of an n-type silicon substrate. Referring to
FIG. 1
a
, there is shown a cross section of a typical MOS transistor that is formed on the surface of a silicon substrate
10
. A layer
12
of gate oxide is first formed over the surface of the substrate
10
, this layer
12
of oxide serves as a stress relieve layer between the gate of the MOS transistor and the silicon surface. A layer of polysilicon or the like is deposited over the layer of gate oxide
12
and patterned and etched to form the structure
14
of the gate electrode. Source and drain regions (
16
and
18
respectively) are then formed self-aligned with and adjacent to the gate electrode
14
by implanting of high-concentration n-type impurities into the surface of the silicon substrate
10
. In the era of ULSI devices, the width of the gate has been reduced to below 0.5 um, the distance between the source and the drain region (the channel length) is correspondingly reduced. This sharp reduction in channel length however leads to a significant increase in the concentration of the electromagnetic field close to drain region
18
where this drain region interfaces with the underlying silicon substrate
10
. This sharp increase may lead to leakage current between the drain region
18
and the surrounding silicon of substrate
10
. In addition, hot carriers can be created in the silicon of the substrate
10
and can gain sufficient energy to penetrate into the layer of gate oxide
12
underneath the gate structure
14
resulting in impacting the threshold voltage between the gate
14
and the substrate
10
. This may lead to current flow between the gate electrode
14
and the underlying substrate
10
.
To counteract the increase in the electric field, the art has implemented the formation of Lightly Doped Drain (LDD) regions
20
and
22
that are shown in
FIG. 1
b
. The LDD regions
20
and
22
form double off-set regions whereby the source and drain regions now contain high n-type impurity concentrations
16
and
18
and low n-type impurity concentrations
20
and
22
. The principle objective of the LDD regions
20
and
22
is to offset the high concentration of the electric field around the drain region
18
. The regions are symmetrically formed around the gate electrode and consist of low-concentrations of n-type impurities
20
and
22
. The profile of the implanted regions
20
and
22
indicates that the impurity concentrations in the p-n junction change gradually thereby extending to the source and drain regions to attenuate the electric field.
With the creation of the LDD regions
20
and
22
, the breakdown between the drain region
18
and the channel region between the source and the drain region has been eliminated. Hot carriers that could affect the threshold voltage are thereby also eliminated. However, the low concentration regions
20
and
22
form high resistivity regions by their nature of being low concentration impurity regions. Since the current flows between the source and drain regions, the regions
20
and
22
are now parasitic resistances that are connected in series between the source and the drain regions. This lowers the drain current and the n-resistance performance of the transistor thereby reducing the performance of the device. Sidewalls
24
and
26
of the gate electrode structure
14
that have been formed on the surfaces of the low-concentration n-source and drain regions further emphasizing this effect. The high electric field that is in effect around the drain region
18
generates hot carriers, some of these carriers may be injected into the lower portion of the sidewall
26
of the drain region
18
. The region of the silicon surface of the n-type impurity
22
becomes depleted of carriers due to the electric field that is created by the hot carriers that have become trapped in the underlying layer of gate oxide
12
. This results in an increase of the threshold voltage of the transistor thereby having a negative effect on the drain characteristics and ultimately on the reliability of the transistor.
The CMOS device can be divided into a low voltage transistor with operating voltages of no larger than about six volts or a high voltage transistor with an operating voltage in excess of thirteen volts. Low voltage transistors are generally used at the logic or intermediate stages of signal processing while high voltage transistors are generally used as current drivers and switches or as serving at input and output stages of the integrated circuit.
The doping for the formation of regions
20
and
22
is typically performed after the gate spac
Chen Jong
Chu Wen-Ting
Jung Lin Chrong
Su Hung-Der
Ackerman Stephen B.
Lattin Christopher
Neibling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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