Integration process on a SOI substrate of a semiconductor...

Details Integration process on a SOI substrate of a semiconductor... Integration process on a SOI substrate of a semiconductor...

2001-12-28

2004-08-31

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S404000, C438S432000

Reexamination Certificate

active

06784042

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an integration process in a SOI substrate of a semiconductor device comprising at least a dielectrically insulated well.
The invention relates, particularly but not exclusively, to a process for integrating a BiCMOS technology device in a SOI (Silicon-On-Insulator) substrate.
2. Description of the Related Art
As it is well known, full electrical insulation for one or more devices may be obtained, for example, by integrating a dielectric trench insulating structure so as to create one or more isolation wells wherein such devices can be formed.
Particularly with devices made in SOI substrates, which devices are characterized by a BOX (Buried OXide) layer providing vertical insulation, a dielectric trench side insulating structure is specifically provided for lateral insulation only.
Thus, continuity from the buried oxide layer to the dielectric trench side insulating structure ensures dielectric insulation of devices integrated in the SOI substrates and formed in suitable wells, known as isolation wells, which are surrounded by the BOX layer and the dielectric trench side insulating structure.
Shown schematically in
FIG. 1
is a portion
1
of a semiconductor device that includes essentially a dielectrically insulated well
2
according to the prior art.
In particular, the semiconductor device portion
1
includes a substrate region
3
, also known as the handle-wafer, which usually provides mechanical support. Where complex devices are integrated, it also serves as an active silicon layer.
Formed onto the substrate region
3
is a buried oxide (BOX) layer
4
which is used for vertical insulation of the well
2
, side insulation thereof being provided by means of a side oxidized region that is covered by a nitride layer
6
and is provided at the edges of the well
2
in dielectric contact with the buried oxide layer
4
.
In particular, the combination of two side oxidized regions
5
with their nitride layers
6
, and the underlying portion of the buried oxide layer
4
, forms a so-called dielectric trench insulating structure
7
which is usually filled with a filling material
8
, usually polysilicon.
The dielectric trench insulating structure
7
defines, inside the well
2
, an integration region
9
(device-wafer) for a variety of components that are thus isolated from the remainder of the semiconductor device.
The surface of the semiconductor device portion
1
should be sufficiently planar to allow the other layers required for integrating components of interest in the well
2
to be grown or deposited. The involved layers may be photoresist, nitride, vapox, oxide, metallization or other layers, for example.
It should be noted here that processes of etching and depositing mutually selective layers are necessary to produce the side insulation, as well as for the planarizing step.
For example, silicon etching to form the dielectric trench insulating structure
7
is to be carried out selectively with respect to the surface layers (such as oxide and/or nitride layers). In particular the presence of the buried oxide layer
4
, typical of SOI substrates, makes a complicated process sequence necessary to avoid etching away or damaging the layer
4
during any of the processing steps required to form the electrically isolated well
2
.
From U.S. Pat. No. 5,811,315 to W. Yindeepol et al., a method of forming dielectric trench insulating structures in SOI substrates is known, which comprises, in particular, a process sequence for integrating and planarizing deep trenches, and is directed to leave the thickness of a field oxide, preliminarily grown over the silicon wafer surface, unaffected.
Reference will be made now to
FIGS. 2A
to
2
O for a description of this known process sequence.
Starting with a SOI substrate
13
formed onto a conventional substrate
11
, and a buried oxide layer
12
(as shown schematically in FIG.
2
A), the following layers are formed in this order: a thick oxide layer
14
(also known as field oxide), being grown preliminarily over the silicon surface of the substrate
13
; a silicon nitride layer
15
, being deposited onto said field oxide
14
; and a (VAPOX or TEOS) deposited oxide layer
16
, acting as a hardmask, which is deposited onto the previously formed layer
15
of silicon nitride.
The silicon nitride layer
15
is used, in particular, to avoid etching the field oxide
14
away during the step of removing the hardmask layer
16
, as later provided after a dielectric insulating trench
17
is formed.
The hardmask layer
16
is purposely coated with a resist layer
18
(as shown schematically in FIG.
2
B), and appropriate openings are formed to the same width as the dielectric trenches
17
to be formed, using photolithographic processes well known to the skilled persons in the art. A step is then carried out of dry etching the layers
16
,
15
and
14
, the etchant chemistry for these layers being selective with respect to the substrate
13
.
Thereafter, the resist layer
18
is removed, and the substrate
13
is dry etched down to the buried oxide layer
12
to form the dielectric trench
17
(as shown schematically in FIG.
2
C).
To remove crystal damages caused during this etching step along the walls of the dielectric trench
17
, a thin oxide layer
19
, known as sacrificial oxide, is grown and subsequently removed (as shown schematically in FIGS.
2
D and
2
E). The thin sacrificial oxide layer
19
is etched using a HF solution. This etching should not be applied for too long, overetching of the buried oxide layer
12
and the field oxide
14
being thus avoided.
A sidewall oxidation process to grow an oxide layer
20
along the sidewalls of the dielectric trench
17
(as shown schematically in FIG.
2
F), and a depositing step of a nitride layer
21
all over the surface of the semiconductor device (as shown schematically in FIG.
2
G), are then carried out.
The nitride layer
21
is next etched away, anisotropically and selectively with respect to the buried oxide layer
12
, but allowed to stay on the sidewall surfaces of the dielectric layer
17
in order to form so-called spacers in contact with the silicon nitride layer
15
(as shown schematically in FIG.
2
H). The nitride layer
21
is instead removed from over the hardmask layer
16
and from the bottom of the dielectric trench
17
.
It should be noted that the deposition of the nitride layer
21
is also directed to prevent etching through the field oxide
14
as the hardmask layer
16
is removed. For the purpose, the thickness of the hardmask layer
16
is originally selected to ensure that a vertical-wall portion of it will survive the various etching steps and provide good covering of the spacer formed by nitride layer
21
, which will serve to keep the side regions of the field oxide
14
intact (as shown schematically in FIG.
2
I).
This means that, during the process operations between the two nitride depositions, HF etchings will be applied to remove any residual oxynitride
22
from the interface of the two nitride layers (
15
and
21
), as shown schematically in FIG.
2
J.
Following a step of anisotropically removing the nitride layer
21
, the resulting trench
23
is filled with a filling material
24
, specifically a polysilicon filling material (as shown schematically in FIG.
2
K).
Thereafter, the polysilicon filling material
24
is removed from the surface, which is an endpoint with respect to the hardmask layer
16
(etching back step), thereby to leave some polysilicon
24
inside the trench
23
(as shown schematically in FIG.
2
L). At this stage, the polysilicon filling material
24
is overetched slightly so that the following cap oxidizing step can be planar with respect to the field oxide
14
.
After this etching back step of the polysilicon filling material
24
, the hardmask layer
16
leftover is removed. It is therefore important to have a robust interface provided between the nitride regions
15
and
21
that is capable of withstanding the protracted exposur

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