Integration process flow for flash devices with low gap fill...

Details Integration process flow for flash devices with low gap fill... Integration process flow for flash devices with low gap fill...

2005-10-18

2009-06-02

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S294000

Reexamination Certificate

active

07541240

ABSTRACT:
A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with the underlying dielectric. A conductive layer overlies the substrate during implantation. A substrate having small polysilicon features in a memory array and large polysilicon features in a peripheral area is accurately planarized using protrusions in the peripheral area and a soft chemical mechanical polishing step that stops when protrusions are removed.

REFERENCES:
patent: 5043940 (1991-08-01), Harari
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5168465 (1992-12-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5198380 (1993-03-01), Harari
patent: 5268318 (1993-12-01), Harari
patent: 5268319 (1993-12-01), Harari
patent: 5297148 (1994-03-01), Harari et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5380672 (1995-01-01), Yuan et al.
patent: 5385630 (1995-01-01), Philipossian et al.
patent: 5389808 (1995-02-01), Arai
patent: 5459091 (1995-10-01), Hwang
patent: 5512505 (1996-04-01), Yuan et al.
patent: 5534456 (1996-07-01), Yuan et al.
patent: 5554553 (1996-09-01), Harari
patent: 5579259 (1996-11-01), Samachisa et al.
patent: 5595924 (1997-01-01), Yuan et al.
patent: 5640032 (1997-06-01), Tomioka
patent: 5654217 (1997-08-01), Yuan et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5677872 (1997-10-01), Samachisa et al.
patent: 5712179 (1998-01-01), Yuan
patent: 5712180 (1998-01-01), Guterman et al.
patent: 5716863 (1998-02-01), Arai
patent: 5747359 (1998-05-01), Yuan et al.
patent: 5756385 (1998-05-01), Yuan et al.
patent: 5786988 (1998-07-01), Harari
patent: 5817580 (1998-10-01), Violette
patent: 5847425 (1998-12-01), Yuan et al.
patent: 5867429 (1999-02-01), Chen et al.
patent: 5883409 (1999-03-01), Guterman et al.
patent: 5891752 (1999-04-01), Losee
patent: 5899736 (1999-05-01), Weigand et al.
patent: 5923976 (1999-07-01), Kim
patent: 5950096 (1999-09-01), Huang et al.
patent: 5965913 (1999-10-01), Yuan et al.
patent: 5966618 (1999-10-01), Sun et al.
patent: 5981335 (1999-11-01), Chi
patent: 5999448 (1999-12-01), Kurihara et al.
patent: 6028336 (2000-02-01), Yuan
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6060360 (2000-05-01), Lin et al.
patent: 6103573 (2000-08-01), Harari et al.
patent: 6151248 (2000-11-01), Harari et al.
patent: 6172395 (2001-01-01), Chen et al.
patent: 6184093 (2001-02-01), Sung
patent: 6208545 (2001-03-01), Leedy
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6235586 (2001-05-01), Au et al.
patent: 6258665 (2001-07-01), Shimizu et al.
patent: 6281075 (2001-08-01), Yuan et al.
patent: 6281077 (2001-08-01), Patelmo et al.
patent: 6295227 (2001-09-01), Sakui et al.
patent: 6297097 (2001-10-01), Jeong
patent: 6326263 (2001-12-01), Hsieh
patent: 6365525 (2002-04-01), Müller
patent: 6391722 (2002-05-01), Koh
patent: 6417051 (2002-07-01), Takebuchi
patent: 6417538 (2002-07-01), Choi
patent: 6455440 (2002-09-01), Jeng
patent: 6455889 (2002-09-01), Sakui
patent: 6461973 (2002-10-01), Hui et al.
patent: 6465323 (2002-10-01), Yu et al.
patent: 6483146 (2002-11-01), Lee et al.
patent: 6512263 (2003-01-01), Yuan et al.
patent: 6529410 (2003-03-01), Han et al.
patent: 6544431 (2003-04-01), Gill et al.
patent: 6548374 (2003-04-01), Chung
patent: 6559008 (2003-05-01), Rabkin et al.
patent: 6562682 (2003-05-01), Chiu et al.
patent: 6614684 (2003-09-01), Shukuri et al.
patent: 6620681 (2003-09-01), Kim et al.
patent: 6642109 (2003-11-01), Lee et al.
patent: 6713385 (2004-03-01), Pipes et al.
patent: 6713834 (2004-03-01), Mori et al.
patent: 6762092 (2004-07-01), Yuan et al.
patent: 6770932 (2004-08-01), Himeno et al.
patent: 6791142 (2004-09-01), Tseng
patent: 6794708 (2004-09-01), Mori
patent: 6838357 (2005-01-01), Chen et al.
patent: 6844586 (2005-01-01), Ding
patent: 6855966 (2005-02-01), Chuang et al.
patent: 6891246 (2005-05-01), Aritome
patent: 6893918 (2005-05-01), Wang et al.
patent: 6894930 (2005-05-01), Chien et al.
patent: 6897517 (2005-05-01), Van Houdt et al.
patent: 6897524 (2005-05-01), Kamiya
patent: 6898121 (2005-05-01), Chien et al.
patent: 6908817 (2005-06-01), Yuan
patent: 7023049 (2006-04-01), Takebuchi et al.
patent: 2002/0048897 (2002-04-01), Hong
patent: 2002/0072197 (2002-06-01), Kang et al.
patent: 2002/0160570 (2002-10-01), Tseng
patent: 2002/0197800 (2002-12-01), Hashimoto et al.
patent: 2003/0015497 (2003-01-01), Gill et al.
patent: 2003/0029839 (2003-02-01), Chou
patent: 2003/0119263 (2003-06-01), Lee et al.
patent: 2004/0084713 (2004-05-01), Hsieh
patent: 2004/0126972 (2004-07-01), Dong et al.
patent: 2004/0191992 (2004-09-01), Ni et al.
patent: 2005/0082614 (2005-04-01), Takehiro
patent: 2005/0106813 (2005-05-01), Lee et al.
patent: 2005/0127473 (2005-06-01), Sakagami
patent: 2005/0199939 (2005-09-01), Lutze et al.
patent: 2006/0134845 (2006-06-01), Pham et al.
patent: 196 17 632 (1997-07-01), None
patent: 1274132 (2003-01-01), None
patent: 1363324 (2003-11-01), None
patent: 05190809 (1993-07-01), None
patent: 2001-135736 (2001-05-01), None
patent: WO 01/24268 (2001-04-01), None
patent: WO 2007/047390 (2007-04-01), None
patent: WO 2007/047390 (2007-04-01), None
“Planarized NVRAM Cell with Self-Aligned BL-BL and WL-BL Isolations”, IBM Technical Disclosure Bulletin, IBM Corp. New York, US, vol. 36, No. 2, Feb. 1, 1993, pp. 375-377.
EPO/ISA, Communication Relating to the Results of the Partial International Search, mailed in corresponding International Application No. PCT/US2006/039931 (published as WO 2007/047390) on Feb. 8, 2007, 5 pages.
EPO/ISA, Notification of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, mailed in corresponding International Application No. PCT/US2006/039931 (published as WO 2007/047390) on Apr. 17, 2007, 17 pages.
Aritome, Seiichi, “Advanced Flash Memory Technology and Trends for File Storage Application,” IEDM Technical Digest, International Electronic Devices Meeting, IEEE, San Francisco, California, Dec. 10-13, 2000, pp. 33.1.1-33.1.4.
Chan, et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,”IEEE Electron Device Letters, vol. EDL-8, No. 3, Mar. 1987, pp. 93-95.
DiMaria et al., “Electrically-alterable read-only-memory using Si-rich SI02injectors and a floating polycrystalline silicon storage layer,”J. Appl. Phys. 52(7), Jul. 1981, pp. 4825-4842.
Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,”IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
Higashitani et al., “Multi-Thickness Dielectric for Semiconductor Memory,” U.S. Appl. No. 11/020,402, filed Dec. 22, 2004, 27 pages.
Hori et al., “A MOSFET with Si-implanted Gate-SiO2Insulator for Nonvolatile Memory Applications,” IEDM 92, Apr. 1992, pp. 469-472.
Lee, Jae-Duk, et al., “Effects of Parasitic Capacitance on NAND Flash Memory Cell Operation,” Non-Volatile Semiconductor Memory Workshop, IEEE, Monterey, California, Aug. 12-16, 2001, pp. 90-92.
Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,”IEEE Journal of Solid State Circuits, vol. 26, No. 4, Apr. 1991, pp. 497-501.
Park et al., “8Gb MLC (Multi-Level Cell) NAND Flash Memory using 63nm Process Technology”, Samsung Electronics, Co., LTD., Semiconductor R & D Center, pp. 1-4, Dec. 15, 2004.
Pham et al., “Low-Voltage, Multiple Thin-Gate Oxide and Low-Resistance Gate Electrode”, U.S. Appl. No. 11/021,693, filed Dec. 22, 2004, 25 pages.
Takeuchi, Y., et al., “A Self-Aligned STI Process Integration for Low Cost and Highly Reliable lGbit Flash Memories,” 1998 Symposium on V

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