Integration of the borderless contact salicide process

Details Integration of the borderless contact salicide process Integration of the borderless contact salicide process

2000-01-24

2001-07-24

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S682000

Reexamination Certificate

active

06265271

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of integrating salicide and borderless contact processes in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, logic products are often produced using salicide (self-aligned silicide) processes in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
In order to shrink cell size, a borderless contact is one of the most important processes in the art. Of major concern is the borderless contact leakage current for shallow junctions, especially at the edge of the shallow trench isolation (STI) regions. It is desired to find a method of integrating the salicide and the borderless contact processes while avoiding the leakage current problem at the STI edge.
U.S. Pat. No. 5,545,581 to Armacost et al teaches depositing a nitride layer over salicide to be used as an etch stop when making a contact. U.S. Pat. No. 5,937,325 to Ishida forms a salicide using two RTA steps, first forming the salicide over a gate, then forming a salicide over the source/drain. U.S. Pat. Nos. 5,719,079 to Yoo et al. and 5,674,781 to Huang et al. teach borderless contact processes but without etch stop layers. U.S. Pat. No. 5,516,726 to Kim et al. discloses an etch stop for a borderless contact process, but no salicide process.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for integrating salicide and borderless contact processes in the fabrication of integrated circuits.
It is a further object of the invention to provide a process for integrating salicide and borderless contact processes while avoiding current leakage at the shallow trench isolation edge in the fabrication of logic circuits.
Yet another object is to provide a process for integrating salicide and borderless contact processes while avoiding current leakage at the shallow trench isolation edge by densifying a nitride liner film to protect the STI edge.
In accordance with the objects of the invention, a method for integrating salicide and borderless contact processes while avoiding current leakage at the shallow trench isolation edge by densifying a nitride liner film to protect the STI edge is achieved. Shallow trench isolation (STI) regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A metal layer is deposited over the gate electrode and associated source and drain regions. A first annealing of the semiconductor substrate transforms the metal layer into a metal silicide layer over the gate electrode and source and drain regions. The metal layer which is not transformed into a metal silicide overlying the dielectric spacers and shallow trench isolation regions is removed. An etch stop layer is deposited over the surface of the semiconductor substrate. A second annealing changes the metal silicide layer to a phase having lower resistance and also densifies the etch stop layer. An interlevel dielectric layer is deposited over the densified etch stop layer. A borderless contact opening is formed through the interlevel dielectric layer and the etch stop layer to one of the source and drain regions and the contact opening is filled with a conducting layer to complete fabrication of the integrated circuit device.


REFERENCES:
patent: 5512778 (1996-04-01), Chung et al.
patent: 5516726 (1996-05-01), Kim et al.
patent: 5545581 (1996-08-01), Armacost et al.
patent: 5674781 (1997-10-01), Huang et al.
patent: 5719079 (1998-02-01), Yoo et al.
patent: 5780348 (1998-06-01), Lin et al.
patent: 5937325 (1999-08-01), Ishida
patent: 6005279 (1999-12-01), Luning
patent: 6071782 (2000-06-01), Maa et al.
patent: 11-345966 (1999-12-01), None

Affiliated with

Also associated with

Rating

Integration of the borderless contact salicide process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integration of the borderless contact salicide process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integration of the borderless contact salicide process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2483843